This repository contains the Simple As Possible Floating Point Unit design based on the IEEE-754 Standard.
☆18Mar 17, 2023Updated 3 years ago
Alternatives and similar repositories for SAP_FPU
Users that are interested in SAP_FPU are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This repo contain the PY-UVM Framework for different RISC-V Cores☆33Sep 16, 2023Updated 2 years ago
- Implementation of RISC-V RV32I☆32Aug 30, 2022Updated 3 years ago
- 📁 Repo for python_splitter Python package. This package can split Images into Train, Test, Validation folders automatically by shuffling…☆11Jan 1, 2024Updated 2 years ago
- ☆15Sep 27, 2022Updated 3 years ago
- Verilog HDL implementation of an ECHO machine and an FIR filter that filters out a specific noise. More details provided in individual fi…☆10Aug 25, 2019Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- This repository contains the design files of RISC-V Pipeline Core☆76May 11, 2023Updated 3 years ago
- A Verilog implementation of a processor cache.☆40Dec 29, 2017Updated 8 years ago
- This source code (in Python) is a preliminary implementation of my quadratic-time positive integer matrix multiplication.☆10Nov 23, 2022Updated 3 years ago
- ☆15Aug 3, 2021Updated 5 years ago
- A simple spidergon network-on-chip with wormhole switching feature☆13Mar 22, 2021Updated 5 years ago
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆66Jul 5, 2024Updated 2 years ago
- Approximate arithmetic circuits for FPGAs☆13Feb 19, 2020Updated 6 years ago
- Cordic fixed point math☆22Jul 17, 2024Updated 2 years ago
- 6-stage dual-issue in-order superscalar risc-v cpu☆14Updated this week
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆14Jul 16, 2026Updated 3 weeks ago
- APB Timer Unit☆14Oct 30, 2025Updated 9 months ago
- ☆22Oct 10, 2018Updated 7 years ago
- 简单的未优化的SRT除法器☆12Jun 16, 2024Updated 2 years ago
- SE(3) exponential map at zero helper for SymPy☆34May 18, 2023Updated 3 years ago
- 5 Day TCL begginer to advanced training workshop by VSD☆20Oct 18, 2023Updated 2 years ago
- Basic floating-point components for RISC-V processors☆12Aug 13, 2017Updated 8 years ago
- Synthesizable and Parameterized Cache Controller in Verilog☆49Jun 13, 2023Updated 3 years ago
- note about IC knowledge☆10Sep 7, 2022Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Adding UVM support to Icarus Verilog (and Verilator in near future) by taking a step-by-step, bottom-up approach.☆24Dec 27, 2022Updated 3 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆15Dec 23, 2022Updated 3 years ago
- NTU Computer Architecture 2021 - CPU with Single issue, L1-cache☆11Jan 24, 2022Updated 4 years ago
- Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. This project was an interview assignment. Work in Progress.☆19Oct 19, 2024Updated last year
- This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…☆21Aug 5, 2023Updated 3 years ago
- APB4 Multiplexor☆15May 10, 2024Updated 2 years ago
- For CPU experiment☆14Feb 23, 2021Updated 5 years ago
- RISC-V Processor Implementation (RV32IM, TileLink-UL)☆27Apr 9, 2026Updated 4 months ago
- Non official pytorch implementation of i-Resnet, invertible residual networks.☆25Mar 16, 2022Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Simulator that maintains coherent caches for 4, 8 and 16 core CMP. Implementation of MSI, MESI, MOSI, MOESI and MOESIF protocols for a b…☆11Jan 6, 2015Updated 11 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆29Dec 26, 2022Updated 3 years ago
- APB Logic☆29Updated this week
- This is a hardware implementation of exact multiply accumulator for 32-bit posit number with es=2☆17Jan 27, 2018Updated 8 years ago
- Computer architecture learning environment using FPGAs☆15May 17, 2021Updated 5 years ago
- 重庆大学计算机学院2018级计算机体系结构cache设计☆11Jan 4, 2021Updated 5 years ago
- A extremely size-optimized RV32I soft processor for FPGA.☆27Jun 19, 2018Updated 8 years ago