nicolavianello95 / RISC-V
Design, verification and ASIC implementation of a complete RISC-V CPU with: five stages pipeline, forwarding, automatic hazard detection, Branch Target Buffer using LRU replacement policy, absolute value custom instruction.
☆13Updated 4 years ago
Related projects ⓘ
Alternatives and complementary repositories for RISC-V
- Verilog Modules and Python Scripts for Creating IP Core Build Directories☆29Updated last year
- APB Logic☆12Updated 8 months ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆26Updated 3 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 2 years ago
- Network on Chip for MPSoC☆25Updated last week
- ☆11Updated last year
- USB -> AXI Debug Bridge☆35Updated 3 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆12Updated 8 months ago
- ArmleoCPU - RISC-V CPU RV64GC, SMP, Linux, Doom. Work in progress to execute first instruction with new feature set☆4Updated 2 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆20Updated last week
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆17Updated last year
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆59Updated 3 years ago
- Reconfigurable Binary Engine☆15Updated 3 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆30Updated 3 years ago
- This repository presents the mixed signal design of a Counter Type/ Ramp Type ADC. The Digital part of the circuit i.e 4- bit counter is …☆9Updated 2 years ago
- A simple, scalable, source-synchronous, all-digital DDR link☆19Updated 2 weeks ago
- Procyon is the brightest star in the constellation of Canis Minor. But it's also the name of my RISC-V out-of-order processor.☆12Updated last year
- AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...☆12Updated 3 years ago
- Hamming ECC Encoder and Decoder to protect memories☆28Updated last month
- Open source process design kit for 28nm open process☆42Updated 6 months ago
- Design and UVM-TB of RISC -V Microprocessor☆13Updated 4 months ago
- TileLink Uncached Lightweight (TL-UL) implementation on Chisel.☆21Updated 3 years ago
- SoC Based on ARM Cortex-M3☆25Updated 5 months ago
- Register-based and RAM-based FIFOs designed in Verilog/System Verilog.☆14Updated 2 months ago
- YSYX RISC-V Project NJU Study Group☆11Updated 2 years ago
- RISC V core implementation using Verilog.☆25Updated 3 years ago
- A configurable general purpose graphics processing unit for☆11Updated 5 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆22Updated last month
- DDR4 Simulation Project in System Verilog☆32Updated 10 years ago
- RISC-V soft-core PEs for TaPaSCo☆15Updated 4 months ago