Alternatives and similar repositories for RISC-V

Users that are interested in RISC-V are comparing it to the libraries listed below

• EngAhmed21 / RISC-V-Processor-with-Pipelining
  Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…
  ☆17Updated 2 years ago
• Youssefmdany / Design-and-UVM-TB-of-RISC-V-Microprocessor
  Design and UVM-TB of RISC -V Microprocessor
  ☆33Updated last year
• Youssefmdany / RISC-V-Single-Cycle-Processor-Integrated-With-a-Cache-Memory-System-From-RTL-To-GDS
  RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS
  ☆11Updated last year
• wanderingnail / AXI_DMA
  ☆20Updated 3 years ago
• iammituraj / skid_buffer
  Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.
  ☆28Updated 3 months ago
• kumarrishav14 / AMBA_APB
  To design test bench of the APB protocol
  ☆18Updated 5 years ago
• mpskex / chisel-npu
  Chisel implementation of Neural Processing Unit for System on the Chip
  ☆26Updated 3 weeks ago
• srishis / DMA8237A_VERIF
  Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench
  ☆16Updated 5 years ago
• openhwgroup / core-v-mcu-uvm
  CORE-V MCU UVM Environment and Test Bench
  ☆26Updated last year
• pulp-platform / axi2apb
  ☆22Updated 5 years ago
• StanfordAHA / AhaM3SoC
  SoC Based on ARM Cortex-M3
  ☆37Updated 8 months ago
• Youssefmdany / 10-Gigabit-Ethernet-MAC-Core-UVM-Verification-
  10 Gigabit Ethernet MAC Core UVM Verification
  ☆17Updated 2 years ago
• shrutiprakashgupta / RISCV_Formal_Verification
  Formal Verification of RISC V IM Processor
  ☆10Updated 3 years ago
• atfox272 / AXI4-Interconnect
  RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…
  ☆24Updated 11 months ago
• PacoReinaCampo / MPSoC-DMA
  Direct Access Memory for MPSoC
  ☆13Updated 2 weeks ago
• crusader2000 / PCIE-Transaction-Layer-Verification
  PCIe System Verilog Verification Environment developed for PCIe course
  ☆13Updated last year
• avikram2 / RISCVPipelinedProcessor
  Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…
  ☆14Updated 3 years ago
• merledu / azadi-soc
  Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.
  ☆32Updated 2 years ago
• Anjali-287 / Synchronous-FIFO-UVM-TB
  UVM Testbench for synchronus fifo
  ☆19Updated 5 years ago
• kumarrishav14 / arm_watchdog
  Verification IP for Watchdog
  ☆12Updated 4 years ago
• RClabiisc / I2SRV32-V-v1
  Reconfigurable Computing Lab, DESE, Indian Institiute of Science
  ☆32Updated last year
• adibis / Interrupt_Controller
  An 8 input interrupt controller written in Verilog.
  ☆28Updated 13 years ago
• ShonTaware / LowPower
  Various low power labs using sky130
  ☆13Updated 4 years ago
• jay16udani / ECE745_LC3_Verification
  North Carolina State University: ECE 745 : Project: LC3 Microcontroller Functional Verification using SystemVerilog
  ☆11Updated 8 years ago
• PacoReinaCampo / MPSoC-DV
  Multi-Processor System on Chip verified with UVM/OSVVM/FV
  ☆35Updated 2 weeks ago
• pulp-platform / axi_llc
  ☆33Updated 2 months ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆32Updated 7 years ago
• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 6 years ago
• RoaLogic / ahb3lite_apb_bridge
  Parameterised Asynchronous AHB3-Lite to APB4 Bridge.
  ☆47Updated last year
• nguyenquanicd / AllArbiterRTLCode
  RTL code of some arbitration algorithm
  ☆15Updated 6 years ago