MPSU / MIRISCV

Related projects ⓘ

Alternatives and complementary repositories for MIRISCV

• riscv-tests-intro / riscv-tests-intro
  Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"
  ☆32Updated last month
• serge0699 / synth_school_verif_tasks
  Репозиторий заданий и примеров направления функциональной верификации Школы синтеза цифровых схем
  ☆14Updated this week
• NickolayTernovoy / risc-v_awesome_list
  ☆47Updated 3 years ago
• chipdesignschool / systemverilog-homework
  SystemVerilog language-oriented exercises
  ☆37Updated last week
• RomeoMe5 / DDLM
  Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)
  ☆53Updated last year
• FPGA-Systems / fpga-awesome-list
  Полезные ресурсы по тематике FPGA / ПЛИС
  ☆155Updated this week
• yuri-panchul / basics-graphics-music
  FPGA exercise for beginners
  ☆91Updated this week
• EDAMC / DigitalDesignSchool
  DigitalDesignSchool2022/23 repository
  ☆19Updated last year
• MPSU / exAPS
  Архитектуры процессорных систем (старый репозиторий, ранее размещавшийся по адресу github.com/MPSU/APS)
  ☆93Updated 9 months ago
• yuri-panchul / systemverilog-homework
  SystemVerilog language-oriented exercises
  ☆46Updated last week
• zhelnio / schoolRISCV
  CPU microarchitecture, step by step
  ☆164Updated 2 years ago
• MPSU / APS
  Методические материалы по разработке процессора архитектуры RISC-V
  ☆149Updated this week
• DigitalDesignSchool / ce2020labs
  ChipEXPO 2020 Digital Design School Labs
  ☆35Updated 2 years ago
• vlsiexcellence / Static-Timing-Analysis-Full-Course
  Static Timing Analysis Full Course
  ☆43Updated last year
• wyvernSemi / mem_model
  High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model
  ☆22Updated 3 weeks ago
• SergeyBalabaev / Elective-C-Programming-Language
  Материалы по курсу Углубленное изучение языка С (факультатив) для студентов МИЭТ
  ☆11Updated 5 months ago
• vlotnik / uvm_sin_cos_table
  Contains source code for sin/cos table verification using UVM
  ☆20Updated 3 years ago
• johan92 / verilog-coding-style
  Verilog (SystemVerilog) coding style
  ☆39Updated 5 years ago
• FPGA-InsideOut / hdlgadgets
  human-in-the-loop HDL training tool
  ☆33Updated 8 months ago
• MIPSfpga / digital-design-lab-manual
  Digital Design Labs
  ☆23Updated 5 years ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆61Updated last year
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆99Updated this week
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆50Updated 4 years ago
• LukiLeu / FPGA_ADC
  An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components
  ☆41Updated 3 years ago
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆105Updated this week
• AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop
  Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
  ☆49Updated 2 years ago
• hypernyan / eth_vlg
  ☆53Updated 2 years ago
• hurisson / pyuvm_primer
  Examples for using pyuvm
  ☆14Updated 5 months ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆52Updated last week
• MahmouodMagdi / Clock-Domain-Crossing-Synchronizers
  Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…
  ☆45Updated 6 months ago