MPSU / MIRISCV
Открытое RISC-V процессорное ядро MIRISCV для образовательных целей
☆11Updated 7 months ago
Related projects ⓘ
Alternatives and complementary repositories for MIRISCV
- Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"☆32Updated 2 months ago
- Репозиторий заданий и примеров направления функциональной верификации Школы синтеза цифровых схем☆14Updated last week
- ☆47Updated 3 years ago
- Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)☆53Updated last year
- SystemVerilog language-oriented exercises☆37Updated 2 weeks ago
- FPGA exercise for beginners☆90Updated this week
- DigitalDesignSchool2022/23 repository☆19Updated last year
- Полезные ресурсы по тематике FPGA / ПЛИС☆156Updated last week
- SystemVerilog language-oriented exercises☆48Updated 2 weeks ago
- ChipEXPO 2020 Digital Design School Labs☆35Updated 2 years ago
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆22Updated last month
- CPU microarchitecture, step by step☆164Updated 2 years ago
- Методические материалы по разработке процессора архитектуры RISC-V☆153Updated this week
- Архитектуры процессорных систем (старый репозиторий, ранее размещавшийся по адресу github.com/MPSU/APS)☆93Updated 9 months ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆62Updated last year
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆40Updated 3 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆45Updated 7 months ago
- Static Timing Analysis Full Course☆43Updated last year
- Contains source code for sin/cos table verification using UVM☆20Updated 3 years ago
- SDRAM controller for MIPSfpga+ system☆20Updated 4 years ago
- Материалы по курсу Углубленное изучение языка С (факультатив) для студентов МИЭТ☆11Updated 6 months ago
- UART -> AXI Bridge☆57Updated 3 years ago
- Verilog (SystemVerilog) coding style☆40Updated 5 years ago
- Digital Design Labs☆23Updated 5 years ago
- A fast high-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC☆50Updated 3 years ago
- FPGA exercise for beginners☆30Updated 2 weeks ago
- ☆53Updated 2 years ago
- Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.☆8Updated 9 months ago
- human-in-the-loop HDL training tool☆33Updated 8 months ago
- A set of Wishbone Controlled SPI Flash Controllers☆76Updated 2 years ago