estufa-cin-ufpe / RISC-V-PipelineLinks
32-bit 5-stage pipelined RISC-V processor in SystemVerilog
☆19Updated last year
Alternatives and similar repositories for RISC-V-Pipeline
Users that are interested in RISC-V-Pipeline are comparing it to the libraries listed below
Sorting:
- A Verilog based 5-stage fully functional pipelined RISC-V Processor code.☆41Updated 4 years ago
- This repository contains the design files of RISC-V Pipeline Core☆45Updated 2 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆60Updated 4 months ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆97Updated 3 weeks ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆93Updated last year
- Implementing Different Adder Structures in Verilog☆70Updated 5 years ago
- Basic RISC-V Test SoC☆128Updated 6 years ago
- Generic Register Interface (contains various adapters)☆120Updated 8 months ago
- DDR2 memory controller written in Verilog☆78Updated 13 years ago
- Simple 8-bit UART realization on Verilog HDL.☆105Updated last year
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆110Updated 2 weeks ago
- An implementation of the CORDIC algorithm in Verilog.☆96Updated 6 years ago
- The multi-core cluster of a PULP system.☆97Updated this week
- RISC-V Verification Interface☆92Updated this week
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆64Updated 5 years ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆123Updated last year
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆49Updated 11 months ago
- A Single Cycle Risc-V 32 bit CPU☆46Updated 2 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆105Updated 3 weeks ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆79Updated last year
- Verilog/SystemVerilog Guide☆66Updated last year
- Physical Design Flow from RTL to GDS using Opensource tools.☆102Updated 4 years ago
- This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other detai…☆24Updated 6 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆67Updated last year
- Single-Cycle RISC-V Processor in systemverylog☆22Updated 6 years ago
- This repository contains the design files of RISC-V Single Cycle Core☆47Updated last year
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆130Updated 5 years ago
- 32 bit RISC-V CPU implementation in Verilog☆28Updated 3 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆89Updated last week
- Verilog digital signal processing components☆141Updated 2 years ago