Alternatives and similar repositories for tutorial

Users that are interested in tutorial are comparing it to the libraries listed below

• chinthacharan / DV-Interview-Prep-Guide
  Design Verification Engineer interview preparation guide.
  ☆28Updated 2 weeks ago
• Youssefmdany / RISC-V-Single-Cycle-Processor-Integrated-With-a-Cache-Memory-System-From-RTL-To-GDS
  RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS
  ☆11Updated 11 months ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆57Updated last year
• ShonTaware / SRAM_SKY130
  Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
  ☆73Updated 4 years ago
• EngAhmed21 / RISC-V-Processor-with-Pipelining
  Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…
  ☆14Updated last year
• snbk001 / 100DaysofRTL
  100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…
  ☆35Updated 2 years ago
• vlsiexcellence / Digital-ASIC-Design-Projects-
  Verilog Design, Simulation & Synthesis of Digital ASIC Projects
  ☆15Updated 2 years ago
• Noman-10xe / AXI-DMA-Verification
  Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM
  ☆35Updated 3 weeks ago
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆96Updated last month
• vsdip / vsdsram_sky130
  ☆41Updated 3 years ago
• mbits-mirafra / UVMCourse
  Structured UVM Course
  ☆45Updated last year
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆67Updated 4 years ago
• kerimturak / tcore-rv32imc
  ☆12Updated 4 months ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆41Updated 4 years ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆53Updated last year
• Suntrakanesh / System-Verilog-bootcamp
  System Verilog BootCamp
  ☆25Updated 3 years ago
• semiDESIgner / 50daysRTLcode
  ☆17Updated 2 years ago
• JonathanJing / Asynchronous-FIFO
  Asynchronous fifo in verilog
  ☆35Updated 9 years ago
• shariethernet / Physical-Design-with-OpenLANE-using-SKY130-PDK
  This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…
  ☆46Updated 4 years ago
• The-OpenROAD-Project / megaboom
  ☆28Updated 2 weeks ago
• hanysalah / Design-Pattern-in-SV
  This repo is created to include illustrative examples on object oriented design pattern in SV
  ☆59Updated 2 years ago
• bensampson5 / libsv
  An open source, parameterized SystemVerilog digital hardware IP library
  ☆28Updated last year
• ShashankSirohiya / 100DaysOfRtl
  I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
  ☆23Updated 2 years ago
• nickson-jose / vsdstdcelldesign
  This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…
  ☆73Updated 4 years ago
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆30Updated 2 months ago
• pulp-platform / common_verification
  SystemVerilog modules and classes commonly used for verification
  ☆50Updated 6 months ago
• chipsalliance / uvm-verilator
  ☆97Updated last year
• Youssefmdany / Design-and-UVM-TB-of-RISC-V-Microprocessor
  Design and UVM-TB of RISC -V Microprocessor
  ☆23Updated last year
• mbits-mirafra / axi4_avip
  ☆33Updated 2 months ago
• omega-rg / Cache-Controller
  Two Level Cache Controller implementation in Verilog HDL
  ☆51Updated 5 years ago