Alternatives and similar repositories for tutorial

Users that are interested in tutorial are comparing it to the libraries listed below

• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆59Updated last year
• chinthacharan / DV-Interview-Prep-Guide
  Design Verification Engineer interview preparation guide.
  ☆38Updated 2 months ago
• Noman-10xe / AXI-DMA-Verification
  Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM
  ☆37Updated 2 months ago
• Youssefmdany / RISC-V-Single-Cycle-Processor-Integrated-With-a-Cache-Memory-System-From-RTL-To-GDS
  RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS
  ☆11Updated last year
• hanysalah / Design-Pattern-in-SV
  This repo is created to include illustrative examples on object oriented design pattern in SV
  ☆60Updated 2 years ago
• EngAhmed21 / RISC-V-Processor-with-Pipelining
  Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…
  ☆15Updated last year
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆97Updated 3 months ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆42Updated 4 years ago
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆70Updated 4 years ago
• snbk001 / 100DaysofRTL
  100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…
  ☆35Updated 2 years ago
• mbits-mirafra / UVMCourse
  Structured UVM Course
  ☆50Updated last year
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆30Updated 4 months ago
• kerimturak / tcore-rv32imc
  ☆13Updated 6 months ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆54Updated last year
• mayurkubavat / SystemVerilog
  SystemVerilog examples and projects
  ☆19Updated 3 months ago
• ShonTaware / SRAM_SKY130
  Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
  ☆78Updated 4 years ago
• mbits-mirafra / axi4_avip
  ☆37Updated 4 months ago
• RoaLogic / ahb3lite_apb_bridge
  Parameterised Asynchronous AHB3-Lite to APB4 Bridge.
  ☆45Updated last year
• yuravg / uvm_tb_cross_bar
  SystemVerilog UVM testbench example
  ☆34Updated last year
• semiDESIgner / 50daysRTLcode
  ☆17Updated 2 years ago
• vlsiexcellence / Digital-ASIC-Design-Projects-
  Verilog Design, Simulation & Synthesis of Digital ASIC Projects
  ☆16Updated 2 years ago
• pulp-platform / common_verification
  SystemVerilog modules and classes commonly used for verification
  ☆50Updated 9 months ago
• kumarraj5364 / AMBA-APB-PROTOCOL
  RTL Design and Verification
  ☆16Updated 4 years ago
• vsdip / vsdsram_sky130
  ☆43Updated 3 years ago
• abarajithan11 / cocotb-example
  ☆12Updated 3 years ago
• aignacio / nox
  RISC-V Nox core
  ☆68Updated 2 months ago
• asveske / apb_vip
  APB VIP (UVM)
  ☆15Updated 7 years ago
• vlsiexcellence / Static-Timing-Analysis-Full-Course
  Static Timing Analysis Full Course
  ☆60Updated 2 years ago
• Shehab-Naga / ddr5_phy
  DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision
  ☆66Updated last year
• alice820621 / SystemVerilog-Implementation-of-DDR3-Controller
  The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…
  ☆22Updated 7 years ago