vinayrayapati / iiitb_rv32i
☆13Updated 2 years ago
Alternatives and similar repositories for iiitb_rv32i:
Users that are interested in iiitb_rv32i are comparing it to the libraries listed below
- ☆17Updated 2 years ago
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆9Updated 6 months ago
- 5 Day TCL begginer to advanced training workshop by VSD☆16Updated last year
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆21Updated last year
- Architectural design of data router in verilog☆28Updated 5 years ago
- ☆12Updated this week
- ☆13Updated last year
- This repo is created to include illustrative examples on object oriented design pattern in SV☆55Updated last year
- 2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…☆14Updated 10 months ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆32Updated 2 years ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆23Updated 3 years ago
- ☆27Updated 10 months ago
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆22Updated 11 months ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆66Updated 3 years ago
- ☆15Updated 7 months ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆54Updated 2 years ago
- This repository contains all the information studied and created during the [Advanced Physical Design Using OpenLANE / SKY130](https://ww…☆16Updated 2 years ago
- Implementation of RISC-V RV32I☆17Updated 2 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆28Updated 2 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆37Updated 3 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆43Updated 3 years ago
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆37Updated 3 years ago
- UVM and System Verilog Manuals☆39Updated 6 years ago
- Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog☆24Updated 2 years ago
- ☆12Updated 7 months ago
- IEEE Executive project for the year 2021-2022☆8Updated 2 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆58Updated 2 months ago
- Static Timing Analysis Full Course☆47Updated 2 years ago