☆15Sep 27, 2022Updated 4 years ago
Alternatives and similar repositories for iiitb_rv32i
Users that are interested in iiitb_rv32i are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A vision transformer based framework for classifying executable images as benign or malicious☆11Mar 19, 2024Updated 2 years ago
- Implementation of RISC-V RV32I☆36Aug 30, 2022Updated 4 years ago
- ☆20Sep 16, 2022Updated 4 years ago
- VLSI Design of an 8 x 2 SRAM Array | Cadence Virtuoso☆12Feb 10, 2020Updated 6 years ago
- 5 Day TCL begginer to advanced training workshop by VSD☆20Oct 18, 2023Updated 3 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- This project is about building a high FOM 2.4 GHz LNA for Bluetooth Low-Energy (BLE) Standards, using 45nm CMOS technology.☆18Mar 17, 2019Updated 7 years ago
- Advanced CLI tool for automating Machine Learning (AutoML) using state-of-the-art deep learning models to apply transfer learning with mu…☆19Nov 1, 2026Updated last week
- Course notes from my EE degree and other occasional writeups☆13Apr 19, 2017Updated 9 years ago
- ☆16May 8, 2018Updated 8 years ago
- Verilog description of the Risc-V processor☆10Mar 11, 2019Updated 7 years ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆29Oct 31, 2021Updated 5 years ago
- This repository contains the Simple As Possible Floating Point Unit design based on the IEEE-754 Standard.☆18Mar 17, 2023Updated 3 years ago
- AMBA bus lecture material☆11Jan 21, 2020Updated 6 years ago
- This repository contains the verilog code files of Single Cycle RISC-V architecture☆47Dec 5, 2019Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆87Oct 28, 2023Updated 3 years ago
- Integer Multiplier Generator for Verilog☆27Jul 4, 2025Updated last year
- SDN Controller Test (ONOS, OpenDaylight, RouteFlow, OpenStack-Neutron+ODL, and Etc.....)☆11Aug 29, 2025Updated last year
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆56Feb 22, 2022Updated 4 years ago
- This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.☆35Feb 21, 2019Updated 7 years ago
- ☆15Aug 3, 2021Updated 5 years ago
- This repository contains the design files of RISC-V Pipeline Core☆78May 11, 2023Updated 3 years ago
- A GUI for AnyPS5: unwrap, relink and launch your own PS5 dumps on Windows, Linux and macOS, with every relinker option, runtime variable …☆16Oct 30, 2026Updated last week
- This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-…☆11Jul 19, 2022Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- A small and simple rv32i core written in Verilog☆19Jul 29, 2022Updated 4 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆40Jul 23, 2023Updated 3 years ago
- In this VLSI design course, we explored topics such as HLS programming, combination circuits, sequential circuits, and a capstone project…☆13Jul 23, 2024Updated 2 years ago
- A FIFO or Queue is an array of memory commonly used in hardware to transfer transfer data between two circuits with different clocks. The…☆16Nov 5, 2017Updated 9 years ago
- Project in Course named DESIGN AND IMPLEMENTATION OF COMMUNICATION PROTOCOLS in FCU☆17Oct 18, 2014Updated 12 years ago
- Understanding Physical Verification using open source tools such as Magic and Netgen☆12Oct 18, 2022Updated 4 years ago
- ☆24Sep 17, 2024Updated 2 years ago
- Design and Simulation of 1K * 32 bit SRAM memory design.☆24Dec 15, 2021Updated 4 years ago
- Starting my 100 days verilog RTL, and basic system verilog coding challenge from , 21 may 2024☆28Mar 20, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Official implementation of Look-Up Tables Logic Neural Networks (LLNNs)☆13Apr 8, 2026Updated 6 months ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆33Jun 27, 2022Updated 4 years ago
- Pipelined RISC-V CPU☆28Jun 9, 2021Updated 5 years ago
- Synchronous FIFO Testbench☆12Apr 17, 2022Updated 4 years ago
- Research about dataflow architecture☆15Nov 30, 2023Updated 2 years ago
- ☆25Dec 8, 2021Updated 4 years ago
- Parallel implementation of Smith–Waterman using OpenMP☆10Oct 28, 2020Updated 6 years ago