This repository contains the verilog code files of Single Cycle RISC-V architecture
☆43Dec 5, 2019Updated 6 years ago
Alternatives and similar repositories for SIngle-Cycle-RISC-V-In-Verilog
Users that are interested in SIngle-Cycle-RISC-V-In-Verilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆14Sep 27, 2022Updated 3 years ago
- This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…☆21Aug 5, 2023Updated 2 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆17Jun 24, 2020Updated 6 years ago
- This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other detai…☆45Mar 22, 2019Updated 7 years ago
- Generate SystemVerilog/UVM block level testbench setup with python script☆11Oct 3, 2017Updated 8 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆14Aug 3, 2021Updated 4 years ago
- Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation☆14Nov 28, 2019Updated 6 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆149Oct 2, 2025Updated 9 months ago
- 32 bit RISC-V CPU implementation in Verilog☆34Feb 9, 2022Updated 4 years ago
- Verilog module for I2C Master, up to 16 bit sub addr, 7bit slave address, and multiple byte read/write capable☆27Mar 3, 2026Updated 3 months ago
- Verilog implementation of a simple riscv cpu☆19Oct 28, 2021Updated 4 years ago
- This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codeba…☆23May 4, 2024Updated 2 years ago
- Updated version of the XUP Workshops☆13Aug 10, 2018Updated 7 years ago
- 单周期CPU设计与实现☆15Dec 30, 2022Updated 3 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- ☆21Dec 3, 2025Updated 6 months ago
- This repository implements a scaled-down LLaMA 2-like model on an ARM Cortex-M3 soft core, with a custom systolic array RTL module for ef…☆15Jun 25, 2025Updated last year
- Exploring the Ed25519 (FPGA) design space.☆18Nov 23, 2017Updated 8 years ago
- Approximate convex decomposition(ACD)☆10Sep 9, 2023Updated 2 years ago
- The game 2048 (for Turbo Pascal, Free Pascal and TMT Pascal)☆17Jul 26, 2022Updated 3 years ago
- 16 bit serial multiplier in SystemVerilog☆13Oct 13, 2018Updated 7 years ago
- UART implementation using verilog☆37Feb 14, 2023Updated 3 years ago
- Elgamal's over Elliptic Curves☆20Dec 22, 2018Updated 7 years ago
- Dockerized dev environment for the xv6 os☆10Jan 29, 2023Updated 3 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Verilog implementation of a RISC-V core☆141Oct 11, 2018Updated 7 years ago
- This code is a python implementation of the paper, "Illumination Estimation for Nature Preserving Low Light Image Enhancement",in 2020.☆12Jan 12, 2021Updated 5 years ago
- Wikipedia article dataset☆12May 10, 2019Updated 7 years ago
- Deep Learning Experiments Motivated from Fastai Course☆14Jan 2, 2019Updated 7 years ago
- 中央氣象局觀測資料查詢系統(CWB Observation Date Inquire System, CODiS)的爬蟲☆11Dec 18, 2018Updated 7 years ago
- 5 Day TCL begginer to advanced training workshop by VSD☆20Oct 18, 2023Updated 2 years ago
- Deep Reinforcement Learning for Dialogue Generation using SEQ2SEQ model☆11Feb 23, 2021Updated 5 years ago
- Quite OK image compression Verilog implementation☆23Nov 27, 2024Updated last year
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆29Oct 31, 2021Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Simulating Turing machines for the Busy Beaver game☆13Feb 12, 2022Updated 4 years ago
- Implementation of RISC-V RV32I☆30Aug 30, 2022Updated 3 years ago
- A C17 compiler written in Rust☆13Jul 16, 2025Updated 11 months ago
- Pytorch implementation of additive margin softmax loss☆12Aug 5, 2021Updated 4 years ago
- A neural branch predictor tested using CPU emulator, testing both supervised learning and reinforcement learning (for COS 583: Great Mome…☆15May 17, 2017Updated 9 years ago
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆36Feb 21, 2024Updated 2 years ago
- Bare-metal Forth implementation for RISC-V☆63Feb 9, 2024Updated 2 years ago