merledu / SIngle-Cycle-RISC-V-In-VerilogLinks
This repository contains the verilog code files of Single Cycle RISC-V architecture
☆33Updated 5 years ago
Alternatives and similar repositories for SIngle-Cycle-RISC-V-In-Verilog
Users that are interested in SIngle-Cycle-RISC-V-In-Verilog are comparing it to the libraries listed below
Sorting:
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆130Updated 5 years ago
- This repository contains the design files of RISC-V Single Cycle Core☆49Updated last year
- This repository contains the design files of RISC-V Pipeline Core☆47Updated 2 years ago
- Simple RiscV core for academic purpose.☆22Updated 5 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆96Updated last year
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆102Updated last month
- Basic RISC-V Test SoC☆132Updated 6 years ago
- 32 bit RISC-V CPU implementation in Verilog☆28Updated 3 years ago
- AXI4 and AXI4-Lite interface definitions☆94Updated 4 years ago
- Simple 8-bit UART realization on Verilog HDL.☆106Updated last year
- An AXI4 crossbar implementation in SystemVerilog☆160Updated last week
- A simple implementation of a UART modem in Verilog.☆137Updated 3 years ago
- Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in …☆133Updated 2 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆67Updated last year
- This repository contains the Simple As Possible Floating Point Unit design based on the IEEE-754 Standard.☆18Updated 2 years ago
- This is a verilog implementation of 4x4 systolic array multiplier☆55Updated 4 years ago
- Generic FIFO implementation with optional FWFT☆58Updated 5 years ago
- Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Squ…☆56Updated 10 months ago
- A Single Cycle Risc-V 32 bit CPU☆47Updated 2 years ago
- Various caches written in Verilog-HDL☆124Updated 10 years ago
- IEEE 754 floating point unit in Verilog☆138Updated 9 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆115Updated this week
- A classic 5-stage pipeline MIPS 32-bit processor. solve every hazard with stall☆49Updated 4 months ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆136Updated last week
- Verilog for a SECDED Hsaio ECC and a DEC ECC. Power, delay, and area are compared for Berkeley MASIC EEW241B - Advanced Digital Integrate…☆45Updated 10 years ago
- ☆59Updated 4 years ago
- Physical Design Flow from RTL to GDS using Opensource tools.☆103Updated 4 years ago
- A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL☆84Updated 5 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆64Updated 5 years ago
- An Open-Source Design and Verification Environment for RISC-V☆83Updated 4 years ago