merledu / SIngle-Cycle-RISC-V-In-Verilog
This repository contains the verilog code files of Single Cycle RISC-V architecture
☆21Updated 5 years ago
Alternatives and similar repositories for SIngle-Cycle-RISC-V-In-Verilog:
Users that are interested in SIngle-Cycle-RISC-V-In-Verilog are comparing it to the libraries listed below
- Simple RiscV core for academic purpose.☆22Updated 4 years ago
- This repository contains the design files of RISC-V Pipeline Core☆35Updated last year
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆76Updated last year
- 32 bit RISC-V CPU implementation in Verilog☆25Updated 2 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆60Updated 7 months ago
- Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in …☆128Updated 2 years ago
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆122Updated 5 years ago
- ☆33Updated last year
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆58Updated 2 months ago
- Simple 8-bit UART realization on Verilog HDL.☆93Updated 8 months ago
- IEEE 754 floating point unit in Verilog☆133Updated 8 years ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆29Updated 8 months ago
- Pipelined RISC-V CPU☆22Updated 3 years ago
- Simple runtime for Pulp platforms☆39Updated this week
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆123Updated this week
- 64-bit multicore Linux-capable RISC-V processor☆83Updated 4 months ago
- This repository contains the design files of RISC-V Single Cycle Core☆32Updated last year
- This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…☆77Updated 4 years ago
- ☆31Updated last year
- Open source ISS and logic RISC-V 32 bit project☆41Updated last month
- An open source CPU design and verification platform for academia☆93Updated 4 years ago
- 32-bit soft RISCV processor for FPGA applications☆14Updated last year
- A simple implementation of a UART modem in Verilog.☆115Updated 3 years ago
- Simple 3-stage pipeline RISC-V processor☆137Updated 7 months ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆114Updated last week
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated 10 months ago
- Various caches written in Verilog-HDL☆114Updated 9 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆57Updated last month
- Generic Register Interface (contains various adapters)☆103Updated 3 months ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆204Updated 4 years ago