Alternatives and similar repositories for SIngle-Cycle-RISC-V-In-Verilog

Users that are interested in SIngle-Cycle-RISC-V-In-Verilog are comparing it to the libraries listed below

• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆102Updated 4 years ago
• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆49Updated this week
• ultraembedded / core_uriscv
  Another tiny RISC-V implementation
  ☆59Updated 4 years ago
• leros-dev / leros
  A Tiny Processor Core
  ☆114Updated 3 months ago
• emilbiju / emil-risc-v
  32 bit RISC-V CPU implementation in Verilog
  ☆32Updated 3 years ago
• lowRISC / muntjac
  64-bit multicore Linux-capable RISC-V processor
  ☆97Updated 6 months ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆55Updated 7 months ago
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆75Updated last year
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆122Updated 3 months ago
• 4a1c0 / RV32i-Verilog
  Simple RiscV core for academic purpose.
  ☆22Updated 5 years ago
• riscv / riscv-test-env
  ☆50Updated last month
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆132Updated 3 weeks ago
• carlosedp / chiselv
  A RISC-V Core (RV32I) written in Chisel HDL
  ☆105Updated last week
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆81Updated 7 months ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆109Updated last week
• hell03end / verilog-uart
  Simple 8-bit UART realization on Verilog HDL.
  ☆110Updated last year
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆98Updated last year
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆62Updated last year
• tomverbeure / mr1
  MR1 formally verified RISC-V CPU
  ☆53Updated 6 years ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆164Updated 5 years ago
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆34Updated last week
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆186Updated last month
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆62Updated 2 weeks ago
• chipsalliance / fasm
  FPGA Assembly (FASM) Parser and Generator
  ☆97Updated 3 years ago
• AleksandarKostovic / Riscy-SoC
  Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
  ☆80Updated 6 years ago
• drom / awesome-riscv
  😎 A curated list of awesome RISC-V implementations
  ☆138Updated 2 years ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆66Updated last week
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆72Updated 5 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆177Updated 6 months ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆125Updated 7 years ago