This repository contains the verilog code files of Single Cycle RISC-V architecture
☆40Dec 5, 2019Updated 6 years ago
Alternatives and similar repositories for SIngle-Cycle-RISC-V-In-Verilog
Users that are interested in SIngle-Cycle-RISC-V-In-Verilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Implementation of a RISC-V CPU in Verilog.☆17Mar 2, 2025Updated last year
- This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…☆20Aug 5, 2023Updated 2 years ago
- This repository contains the design files of RISC-V Single Cycle Core☆81Dec 14, 2023Updated 2 years ago
- RTL blocks compatible with the Rocket Chip Generator☆17Mar 30, 2025Updated last year
- A Single Cycle Risc-V 32 bit CPU☆71Jan 14, 2026Updated 4 months ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆17Jun 24, 2020Updated 5 years ago
- risc-v 单周期和流水线cpu设计， 基于miniRV-1指令集，语言verilog☆11Feb 23, 2023Updated 3 years ago
- Generate SystemVerilog/UVM block level testbench setup with python script☆11Oct 3, 2017Updated 8 years ago
- Open source ISS and logic RISC-V 32 bit project☆60Jan 20, 2026Updated 4 months ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆146Oct 2, 2025Updated 7 months ago
- A program that can losslessly compress and decompress files using Huffman Encoding☆14Dec 19, 2018Updated 7 years ago
- 32 bit RISC-V CPU implementation in Verilog☆34Feb 9, 2022Updated 4 years ago
- Verilog module for I2C Master, up to 16 bit sub addr, 7bit slave address, and multiple byte read/write capable☆27Mar 3, 2026Updated 2 months ago
- A project to perform the VLSI Physical Design Flow steps of partitioning, floorplan, placement and routing.☆13Jun 9, 2021Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codeba…☆18May 4, 2024Updated 2 years ago
- ☆21Dec 3, 2025Updated 5 months ago
- 武汉大学计算机组成与设计课程单周期CPU处理器实现，使用RISC-V语言实现。☆11Mar 14, 2024Updated 2 years ago
- Approximate convex decomposition(ACD)☆10Sep 9, 2023Updated 2 years ago
- The game 2048 (for Turbo Pascal, Free Pascal and TMT Pascal)☆17Jul 26, 2022Updated 3 years ago
- 16 bit serial multiplier in SystemVerilog☆13Oct 13, 2018Updated 7 years ago
- UART implementation using verilog☆37Feb 14, 2023Updated 3 years ago
- Elgamal's over Elliptic Curves☆20Dec 22, 2018Updated 7 years ago
- Verilog implementation of a RISC-V core☆139Oct 11, 2018Updated 7 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- This code is a python implementation of the paper, "Illumination Estimation for Nature Preserving Low Light Image Enhancement",in 2020.☆12Jan 12, 2021Updated 5 years ago
- Wikipedia article dataset☆12May 10, 2019Updated 7 years ago
- Implementation of Number-theoretic transform(NTT) algorithm on FPGA; 快速数论变换(NTT)的FPGA实现，基为2，有两个并行的蝶形单元☆19Sep 16, 2022Updated 3 years ago
- In this repository, I have shared the codes for designs and testbenches, Elaborated Design and Simulation Output for each block of RISC-V…☆27Aug 28, 2024Updated last year
- Digital Component Design course project.☆20Nov 7, 2018Updated 7 years ago
- 5 Day TCL begginer to advanced training workshop by VSD☆19Oct 18, 2023Updated 2 years ago
- RIVES console emulator☆20Sep 30, 2025Updated 7 months ago
- Quite OK image compression Verilog implementation☆23Nov 27, 2024Updated last year
- User-Agent Switcher for Chzzk Anti Grid (Chrome Extension)☆35Jul 3, 2025Updated 10 months ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆26Jul 23, 2023Updated 2 years ago
- A C17 compiler written in Rust☆13Jul 16, 2025Updated 10 months ago
- Pytorch implementation of additive margin softmax loss☆12Aug 5, 2021Updated 4 years ago
- Simple implementation of I2C interface written on Verilog and SystemC☆49Aug 26, 2017Updated 8 years ago
- Training chatbot models with reinforcement learning in ParlAI.☆17Dec 8, 2022Updated 3 years ago
- ☆19Jun 7, 2021Updated 4 years ago
- This fork family includes the 6502 upgraded to 32-bit address bus, in Verilog HDL☆21Feb 16, 2013Updated 13 years ago