Alternatives and similar repositories for RISCV_Single_Cycle_Core

Users that are interested in RISCV_Single_Cycle_Core are comparing it to the libraries listed below

• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆108Updated last year
• AkeelMedina22 / RISC-V-Pipelined-Processor
  A Verilog based 5-stage fully functional pipelined RISC-V Processor code.
  ☆49Updated 4 years ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆115Updated 3 weeks ago
• merldsu / RISCV_Pipeline_Core
  This repository contains the design files of RISC-V Pipeline Core
  ☆52Updated 2 years ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆141Updated 6 years ago
• shivanishah269 / risc-v-core
  This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…
  ☆79Updated last year
• arm-university / VLSI-Fundamentals-Education-Kit
  Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …
  ☆268Updated 3 months ago
• hell03end / verilog-uart
  Simple 8-bit UART realization on Verilog HDL.
  ☆109Updated last year
• arm-university / Advanced-System-on-Chip-Design-Education-Kit
  Design, implement, and test an Arm Cortex-A-based SoCs on FPGA hardware using functional specifications, standard hardware description an…
  ☆114Updated 3 months ago
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆137Updated 3 weeks ago
• AngeloJacobo / FPGA_Book_Experiments
  My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu
  ☆144Updated 4 years ago
• ekb0412 / 100DaysofRTL
  "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
  ☆94Updated 2 years ago
• ben-marshall / uart
  A simple implementation of a UART modem in Verilog.
  ☆155Updated 3 years ago
• snbk001 / Verilog-Design-Examples
  Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…
  ☆152Updated last year
• ash-olakangal / RISC-V-Processor
  Verilog implementation of multi-stage 32-bit RISC-V processor
  ☆126Updated 4 years ago
• ARC-Lab-UF / sv-tutorial
  SystemVerilog Tutorial
  ☆170Updated 4 months ago
• amradel2020 / vlsi_linkedin_index
  This repo provide an index of VLSI content creators and their materials
  ☆157Updated last year
• merldsu / SAP_FPU
  This repository contains the Simple As Possible Floating Point Unit design based on the IEEE-754 Standard.
  ☆18Updated 2 years ago
• mikeroyal / Verilog-SystemVerilog-Guide
  Verilog/SystemVerilog Guide
  ☆72Updated last year
• abdelazeem201 / Cadence-RTL-to-GDSII-Flow
  In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.
  ☆82Updated last year
• arm-university / Introduction-to-SoC-Design-Education-Kit
  Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…
  ☆141Updated 3 months ago
• cepdnaclk / e16-co502-RV32IM-pipeline-implementation-group1
  The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…
  ☆27Updated 3 years ago
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆128Updated last month
• akilm / Physical-Design
  Physical Design Flow from RTL to GDS using Opensource tools.
  ☆106Updated 4 years ago
• Kobzon86 / Convolutional-Neural-Network-using-SystemVerilog
  Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )
  ☆63Updated 10 months ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆94Updated last week
• jasonlin316 / RISC-V-CPU
  A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
  ☆134Updated 5 years ago
• cebarnes / cordic
  An implementation of the CORDIC algorithm in Verilog.
  ☆99Updated 6 years ago
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆187Updated 2 months ago
• dineshannayya / riscduino
  Arduino compatible Risc-V Based SOC
  ☆156Updated last year