iammituraj / pequeno_riscv
Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
☆80Updated last week
Alternatives and similar repositories for pequeno_riscv:
Users that are interested in pequeno_riscv are comparing it to the libraries listed below
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆86Updated last year
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆77Updated last week
- A Verilog based 5-stage fully functional pipelined RISC-V Processor code.☆35Updated 3 years ago
- Simple 8-bit UART realization on Verilog HDL.☆102Updated last year
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆80Updated last week
- Basic RISC-V Test SoC☆122Updated 6 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆133Updated this week
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆24Updated 3 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆57Updated 2 years ago
- This repository contains the design files of RISC-V Single Cycle Core☆42Updated last year
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆65Updated 4 months ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 4 years ago
- Introductory course into static timing analysis (STA).☆90Updated last week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆96Updated last month
- Open source ISS and logic RISC-V 32 bit project☆51Updated last week
- The Open Source Hardware Accelerator for Efficient Neural Network Inference☆46Updated this week
- Generic Register Interface (contains various adapters)☆116Updated 7 months ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆75Updated last year
- Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor☆48Updated 4 months ago
- RISC-V Nox core☆62Updated last month
- HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…☆48Updated 3 months ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- RISC-V Verification Interface☆89Updated 2 months ago
- AXI4 and AXI4-Lite interface definitions☆92Updated 4 years ago
- ☆92Updated last year
- General Purpose AXI Direct Memory Access☆49Updated 11 months ago
- ☆12Updated last month
- An overview of TL-Verilog resources and projects☆78Updated last month
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆57Updated last year
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆62Updated 11 months ago