iammituraj / pequeno_riscv
Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
☆62Updated last week
Alternatives and similar repositories for pequeno_riscv:
Users that are interested in pequeno_riscv are comparing it to the libraries listed below
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆84Updated last year
- Open source ISS and logic RISC-V 32 bit project☆43Updated 3 months ago
- A Verilog based 5-stage fully functional pipelined RISC-V Processor code.☆29Updated 3 years ago
- Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor☆48Updated 2 months ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆65Updated this week
- Pipelined RISC-V RV32I Core in Verilog☆38Updated last year
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆62Updated 3 months ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆24Updated 3 years ago
- Complete tutorial code.☆17Updated 10 months ago
- Simple 8-bit UART realization on Verilog HDL.☆101Updated 10 months ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆55Updated 2 years ago
- Curriculum for a university course to teach chip design using open source EDA tools☆59Updated last year
- Implementation of RISC-V RV32I☆17Updated 2 years ago
- Two Level Cache Controller implementation in Verilog HDL☆41Updated 4 years ago
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆58Updated 4 months ago
- The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…☆38Updated this week
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆48Updated last year
- RISC-V Nox core☆62Updated 7 months ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆72Updated last year
- ☆12Updated last month
- This repository contains the design files of RISC-V Single Cycle Core☆35Updated last year
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆66Updated 3 years ago
- 5 Day TCL begginer to advanced training workshop by VSD☆16Updated last year
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆29Updated 2 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆38Updated 3 years ago
- ☆14Updated last year
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆77Updated last week
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆57Updated 11 months ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆22Updated 9 months ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆66Updated 2 years ago