iammituraj / pequeno_riscvLinks
Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
☆97Updated 2 weeks ago
Alternatives and similar repositories for pequeno_riscv
Users that are interested in pequeno_riscv are comparing it to the libraries listed below
Sorting:
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆91Updated last year
- A Verilog based 5-stage fully functional pipelined RISC-V Processor code.☆40Updated 4 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆65Updated 5 months ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆110Updated 2 weeks ago
- This repository contains the design files of RISC-V Single Cycle Core☆47Updated last year
- Basic RISC-V Test SoC☆125Updated 6 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆89Updated this week
- Simple 8-bit UART realization on Verilog HDL.☆105Updated last year
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆77Updated last year
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆29Updated 2 years ago
- RISC-V Verification Interface☆92Updated 3 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆105Updated 2 weeks ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆25Updated 3 years ago
- Implementation of RISC-V RV32I☆18Updated 2 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆135Updated this week
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆60Updated 4 months ago
- The multi-core cluster of a PULP system.☆97Updated last week
- A Fast, Low-Overhead On-chip Network☆207Updated this week
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆67Updated last year
- ☆95Updated last year
- Open source ISS and logic RISC-V 32 bit project☆53Updated this week
- AXI4 and AXI4-Lite interface definitions☆94Updated 4 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆159Updated last week
- Generic Register Interface (contains various adapters)☆120Updated 8 months ago
- ☆30Updated last year
- ☆12Updated 2 months ago
- A demo system for Ibex including debug support and some peripherals☆67Updated last week
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆62Updated 2 years ago
- Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor☆48Updated 4 months ago
- HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…☆51Updated 4 months ago