iammituraj / pequeno_riscv
Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
☆53Updated 2 weeks ago
Related projects ⓘ
Alternatives and complementary repositories for pequeno_riscv
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆68Updated 11 months ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆50Updated 2 years ago
- Open source ISS and logic RISC-V 32 bit project☆40Updated this week
- ☆26Updated 7 months ago
- ☆52Updated last year
- Pipelined RISC-V RV32I Core in Verilog☆36Updated last year
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆45Updated 7 months ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆22Updated 3 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆27Updated 2 years ago
- PQR5ASM is a RISC-V Assembler compliant with RV32I☆14Updated 3 weeks ago
- RTL development of Quad Serial Peripheral Interface (Quad-SPI) on QuestaSim using SystemVerilog.☆18Updated 2 years ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆69Updated last year
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆62Updated last year
- ☆39Updated 2 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆21Updated last year
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆27Updated 2 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆34Updated 2 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆63Updated 3 years ago
- Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor☆48Updated 4 months ago
- A Verilog based 5-stage fully functional pipelined RISC-V Processor code.☆22Updated 3 years ago
- UART -> AXI Bridge☆57Updated 3 years ago
- Two Level Cache Controller implementation in Verilog HDL☆36Updated 4 years ago
- Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog☆23Updated 2 years ago
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆32Updated 4 months ago
- 5 Day TCL begginer to advanced training workshop by VSD☆16Updated last year
- Complete tutorial code.☆12Updated 6 months ago
- This is full tutorial of UVM (Universal Verification Methodology) for a simple ALU unit☆18Updated 6 years ago
- ☆10Updated 4 months ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆63Updated 3 years ago
- Python Tool for UVM Testbench Generation☆48Updated 6 months ago