Pequeno R5 (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32IM ISA.
☆157Aug 15, 2026Updated this week
Alternatives and similar repositories for pequeno_riscv
Users that are interested in pequeno_riscv are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- PQR5ASM is a RISC-V Assembler compliant with RV32IM☆19Aug 6, 2026Updated last week
- This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog☆30Feb 19, 2025Updated last year
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆18Feb 12, 2024Updated 2 years ago
- Single Cycle CPU using the RV32I Base Instruction set☆22Nov 5, 2025Updated 9 months ago
- Open source ISS and logic RISC-V 32 bit project☆63Jan 20, 2026Updated 6 months ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- RISC-V CPU Core☆443Jun 24, 2025Updated last year
- RTL data structure☆69Apr 23, 2026Updated 3 months ago
- This repository contains the verilog code files of Single Cycle RISC-V architecture☆43Dec 5, 2019Updated 6 years ago
- A 5-stage pipelined, rv32i core with branch prediction and hazard detection☆15Dec 11, 2025Updated 8 months ago
- APB master and slave developed in RTL.☆27Oct 25, 2025Updated 9 months ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆33Jun 27, 2022Updated 4 years ago
- Multi-cycle RISC-V processor with RV32I/E[M] implementation, built during a few days off.☆19Oct 29, 2024Updated last year
- A synthesizable, five-stage, pipelined 32-bit RISC-V processor (implements the RV32I base ISA)☆13Apr 18, 2024Updated 2 years ago
- Implementation of RISC-V RV32I☆33Aug 30, 2022Updated 3 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Beti Elektronik - ddApp -10 FPGA Uygulamaları (Eğitim) Seti☆13Dec 31, 2024Updated last year
- Advanced Architecture Labs with CVA6☆82Jan 16, 2024Updated 2 years ago
- APB UVC ported to Verilator☆11Nov 19, 2023Updated 2 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆137Jul 11, 2025Updated last year
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆277Nov 6, 2024Updated last year
- A Reconfigurable RISC-V Core for Approximate Computing☆132May 30, 2025Updated last year
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆264Aug 11, 2026Updated last week
- My implementation of the RISC-V Single Cycle Processor, based on the Textbook - Digital Design and Computer Architecture: RISC-V Edition …☆48Jun 2, 2023Updated 3 years ago
- Public repository to host our Checker IP written in SVA that is ported to run on open-source Verilator.☆12Mar 31, 2023Updated 3 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Basic RISC-V Test SoC☆206Apr 7, 2019Updated 7 years ago
- RISC-V CPU Core (RV32IM)☆1,765Sep 18, 2021Updated 4 years ago
- LEVEL: Open-source RV32IMC RISC-V processor core with pipelined microarchitecture, cache support, SoC peripherals and verification framew…☆31Jul 6, 2026Updated last month
- Open-source 8×8 INT8 systolic array inference accelerator — from RTL to bitstream☆19Aug 2, 2026Updated 2 weeks ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆122Jun 18, 2026Updated 2 months ago
- ☆14Apr 29, 2024Updated 2 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆231Updated this week
- A Single Cycle Risc-V 32 bit CPU☆76Jan 14, 2026Updated 7 months ago
- An inhouse RISC-V 32-bits CPU☆21Feb 12, 2026Updated 6 months ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Generic Register Interface (contains various adapters)☆141Aug 6, 2026Updated last week
- Functional verification project for the CORE-V family of RISC-V cores.☆711Updated this week
- RTL blocks compatible with the Rocket Chip Generator☆17Mar 30, 2025Updated last year
- ☆15Sep 27, 2022Updated 3 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆133Dec 17, 2023Updated 2 years ago
- ☆13Dec 1, 2024Updated last year
- Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.☆1,735Updated this week