georgeyhere / Toast-RV32i
Pipelined RISC-V RV32I Core in Verilog
☆38Updated last year
Alternatives and similar repositories for Toast-RV32i:
Users that are interested in Toast-RV32i are comparing it to the libraries listed below
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆62Updated last week
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆66Updated 2 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆62Updated 3 months ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆65Updated this week
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆24Updated 3 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆55Updated 2 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆84Updated last year
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆72Updated last year
- Open source ISS and logic RISC-V 32 bit project☆43Updated 3 months ago
- RISCV model for Verilator/FPGA targets☆50Updated 5 years ago
- Simple 8-bit UART realization on Verilog HDL.☆101Updated 10 months ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆57Updated 11 months ago
- Repository gathering basic modules for CDC purpose☆53Updated 5 years ago
- Static Timing Analysis Full Course☆51Updated 2 years ago
- ☆40Updated 3 years ago
- Python Tool for UVM Testbench Generation☆51Updated 10 months ago
- This repo is created to include illustrative examples on object oriented design pattern in SV☆55Updated 2 years ago
- RISC-V Nox core☆62Updated 7 months ago
- A set of Wishbone Controlled SPI Flash Controllers☆79Updated 2 years ago
- UART -> AXI Bridge☆60Updated 3 years ago
- Curriculum for a university course to teach chip design using open source EDA tools☆59Updated last year
- Open-source high performance AXI4-based HyperRAM memory controller☆69Updated 2 years ago
- Basic RISC-V Test SoC☆118Updated 5 years ago
- Introductory course into static timing analysis (STA).☆88Updated 4 months ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 4 years ago
- Control and Status Register map generator for HDL projects☆110Updated last month
- Playing around with Formal Verification of Verilog and VHDL☆54Updated 4 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆65Updated 4 years ago
- Two Level Cache Controller implementation in Verilog HDL☆41Updated 4 years ago