georgeyhere / Toast-RV32iLinks
Pipelined RISC-V RV32I Core in Verilog
☆41Updated 2 years ago
Alternatives and similar repositories for Toast-RV32i
Users that are interested in Toast-RV32i are comparing it to the libraries listed below
Sorting:
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆112Updated last year
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆117Updated last week
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆80Updated last year
- HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…☆88Updated 4 months ago
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆123Updated 4 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆66Updated 3 years ago
- ☆166Updated 3 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆72Updated 9 months ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆157Updated last week
- Curriculum for a university course to teach chip design using open source EDA tools☆110Updated last year
- Basic RISC-V Test SoC☆146Updated 6 years ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆26Updated 3 years ago
- RISC-V Nox core☆68Updated 2 months ago
- A simple DDR3 memory controller☆60Updated 2 years ago
- Open source ISS and logic RISC-V 32 bit project☆58Updated last week
- Introductory course into static timing analysis (STA).☆97Updated 3 months ago
- Static Timing Analysis Full Course☆60Updated 2 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆96Updated this week
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆119Updated 2 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆49Updated 4 years ago
- Simple 8-bit UART realization on Verilog HDL.☆110Updated last year
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆141Updated this week
- ☆13Updated 6 months ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆30Updated 3 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆49Updated 3 years ago
- SystemVerilog Tutorial☆176Updated this week
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆85Updated last year
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆176Updated 10 months ago
- My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu☆149Updated 4 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆63Updated last year