Alternatives and similar repositories for Toast-RV32i:

Users that are interested in Toast-RV32i are comparing it to the libraries listed below

• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆57Updated last month
• AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop
  Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
  ☆51Updated 2 years ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆63Updated 2 years ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆76Updated last year
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆41Updated last month
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆61Updated 3 weeks ago
• omega-rg / Cache-Controller
  Two Level Cache Controller implementation in Verilog HDL
  ☆39Updated 4 years ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆49Updated 5 years ago
• cepdnaclk / e16-co502-RV32IM-pipeline-implementation-group1
  The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…
  ☆21Updated 3 years ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆76Updated 2 years ago
• asinghani / open-eda-course
  Curriculum for a university course to teach chip design using open source EDA tools
  ☆57Updated last year
• MahmouodMagdi / Clock-Domain-Crossing-Synchronizers
  Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…
  ☆53Updated 9 months ago
• dawsonjon / verilog-math
  Mathematical Functions in Verilog
  ☆86Updated 3 years ago
• vsdip / vsdsram_sky130
  ☆40Updated 2 years ago
• kerimturak / tcore-rv32imc
  ☆11Updated last week
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆78Updated 2 months ago
• shivanishah269 / risc-v-core
  This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…
  ☆69Updated last year
• aignacio / nox
  RISC-V Nox core
  ☆62Updated 5 months ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆53Updated 2 years ago
• HDLForBeginners / Examples
  ☆84Updated last year
• hell03end / verilog-uart
  Simple 8-bit UART realization on Verilog HDL.
  ☆92Updated 8 months ago
• lowRISC / ibex-demo-system
  A demo system for Ibex including debug support and some peripherals
  ☆60Updated 4 months ago
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆54Updated 3 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆61Updated 4 years ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆108Updated 5 years ago
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆51Updated 5 years ago
• vlsiexcellence / Verilog-Crash-Course
  Verilog Fundamentals Explained for Beginners and Professionals
  ☆19Updated 2 years ago
• JAYRAM711 / 100-DAYS-OF-RTL
  This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…
  ☆17Updated last year
• NAvi349 / riscv-proc
  32-bit 5-Stage Pipelined RISC V RV32I Core
  ☆34Updated 6 months ago