Pipelined RISC-V RV32I Core in Verilog
☆43Apr 9, 2023Updated 3 years ago
Alternatives and similar repositories for Toast-RV32i
Users that are interested in Toast-RV32i are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆13Jun 9, 2022Updated 4 years ago
- Realtime video processing w/ Gaussian + Sobel Filters targeting Artix-7 FPGA☆41Nov 8, 2021Updated 4 years ago
- Some neorv32 examples for Intel FPGA boards using Quartus II and SEGGER Embedded Studio for RISC-V.☆15Oct 5, 2025Updated 10 months ago
- A hardware-optimized high-quality pseudorandom number generator☆38Jun 6, 2026Updated 2 months ago
- Pipelined 64-bit RISC-V core☆17Mar 7, 2024Updated 2 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆66Jul 5, 2024Updated 2 years ago
- RISC-V Configuration Structure☆41Oct 30, 2024Updated last year
- AXI Formal Verification IP☆25Apr 28, 2021Updated 5 years ago
- ☆21May 8, 2025Updated last year
- The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …☆20Jun 24, 2021Updated 5 years ago
- A 66-order (67 taps) hamming FIR LPF Filter is to be designed with a cutoff frequency of 200 KHZ for a sampling frequency of 1 MHZ☆15Feb 17, 2023Updated 3 years ago
- Dual RISC-V DISC with integrated eFPGA☆18Oct 9, 2021Updated 4 years ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆53Dec 18, 2025Updated 7 months ago
- What better way to learn VHDL, than to do some fractals?☆54Feb 20, 2021Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- BFS maze solving program☆14Nov 18, 2018Updated 7 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆11Dec 14, 2022Updated 3 years ago
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆21Oct 22, 2025Updated 9 months ago
- 5 days (30 hours) is all what took me to learn the basics and design a pipelined RV32I core. Check this article to know more !☆13Feb 2, 2022Updated 4 years ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions☆27Aug 16, 2023Updated 2 years ago
- Verilog HDL implementation of an ECHO machine and an FIR filter that filters out a specific noise. More details provided in individual fi…☆10Aug 25, 2019Updated 6 years ago
- This repository contains the Simple As Possible Floating Point Unit design based on the IEEE-754 Standard.☆18Mar 17, 2023Updated 3 years ago
- A soft multimedia/graphics processor prototype in Chisel 3☆11May 3, 2023Updated 3 years ago
- This source code (in Python) is a preliminary implementation of my quadratic-time positive integer matrix multiplication.☆10Nov 23, 2022Updated 3 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- The Go programming language☆15Aug 27, 2018Updated 7 years ago
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆106Jun 24, 2025Updated last year
- RISC-V Scratchpad☆78Nov 18, 2022Updated 3 years ago
- RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).☆23Jul 23, 2026Updated 2 weeks ago
- Simple UVM testbench development using the uvmtb_template files☆25Jan 16, 2025Updated last year
- ✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.☆39Feb 22, 2026Updated 5 months ago
- ☆11Nov 17, 2025Updated 8 months ago
- Neural Turing Machine for a Multi-Processor System on Chip verified with UVM/OSVVM/FV☆12Updated this week
- Tutorial of a HW design of MicroBlaze using DDR3 RAM on Arty A7 board; DDR3 RAM speed test application☆86Mar 21, 2026Updated 4 months ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Hardware Trojan on a Basis 3 FPGA for Hardware and Embedded Systems Security☆11May 1, 2017Updated 9 years ago
- Wishbone interconnect utilities☆45Feb 23, 2026Updated 5 months ago
- ☆36Nov 4, 2024Updated last year
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆37Dec 30, 2022Updated 3 years ago
- A wishbone controlled FM transmitter hack☆25Jan 16, 2024Updated 2 years ago
- RISC-V microcontroller for embedded, FPGA and ASIC applications☆200Updated this week
- Cordic fixed point math☆22Jul 17, 2024Updated 2 years ago