A Verilog based 5-stage fully functional pipelined RISC-V Processor code.
☆59May 8, 2021Updated 4 years ago
Alternatives and similar repositories for RISC-V-Pipelined-Processor
Users that are interested in RISC-V-Pipelined-Processor are comparing it to the libraries listed below
Sorting:
- A verilog based 5-stage pipelined RISC-V Processor code.☆35Mar 25, 2020Updated 5 years ago
- 32-bit 5-stage pipelined RISC-V processor in SystemVerilog☆34Oct 29, 2023Updated 2 years ago
- This repository contains the design files of RISC-V Pipeline Core☆66May 11, 2023Updated 2 years ago
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆60Jul 5, 2024Updated last year
- A Single Cycle Risc-V 32 bit CPU☆68Jan 14, 2026Updated last month
- APB master and slave developed in RTL.☆22Oct 25, 2025Updated 4 months ago
- This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog☆24Feb 19, 2025Updated last year
- ☆11Mar 12, 2024Updated last year
- Tests for the design flow with Synopsys tools for the implementation of a RISC-V processor.☆26Sep 8, 2024Updated last year
- DMA Project using Verilog HDL☆14Dec 26, 2019Updated 6 years ago
- Verification IP for Watchdog☆12Apr 6, 2021Updated 4 years ago
- Synchronous FIFO Testbench☆11Apr 17, 2022Updated 3 years ago
- System Verilog using Functional Verification☆12Apr 8, 2024Updated last year
- Single-Cycle RISC-V Processor in systemverylog☆25Apr 23, 2019Updated 6 years ago
- This repository contains the design files of RISC-V Single Cycle Core☆81Dec 14, 2023Updated 2 years ago
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆15Mar 30, 2022Updated 3 years ago
- ☆14Sep 27, 2022Updated 3 years ago
- Minimalistic RV32I RISC-V Processor in System Verilog☆21Sep 19, 2023Updated 2 years ago
- 32 bit RISC-V CPU implementation in Verilog☆34Feb 9, 2022Updated 4 years ago
- ☆18Apr 5, 2015Updated 10 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆17Sep 2, 2023Updated 2 years ago
- The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …☆18Jun 24, 2021Updated 4 years ago
- ☆17Feb 16, 2023Updated 3 years ago
- My implementation of the RISC-V Single Cycle Processor, based on the Textbook - Digital Design and Computer Architecture: RISC-V Edition …☆42Jun 2, 2023Updated 2 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆137Oct 2, 2025Updated 5 months ago
- RTL Design and Verification☆18Jan 4, 2021Updated 5 years ago
- Basic RISC-V Test SoC☆176Apr 7, 2019Updated 6 years ago
- Implementing a five-stage pipeline RSIC-V architecture (RV32I Core instruction set) using Verilog HDL. All the functional modules require…☆35Aug 12, 2020Updated 5 years ago
- ☆93Updated this week
- Single Cycle Processor written in SystemVerilog for executing machine code of RISC-V ISA☆28Apr 23, 2023Updated 2 years ago
- AXI4 with a FIFO integrated with VIP☆22Feb 29, 2024Updated 2 years ago
- 5 Day TCL begginer to advanced training workshop by VSD☆19Oct 18, 2023Updated 2 years ago
- Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …☆299May 30, 2025Updated 9 months ago
- Verilog Fundamentals Explained for Beginners and Professionals☆20Jan 15, 2023Updated 3 years ago
- RISC-V SOC (both single and pipeline) implemented in Verilog. Passed all test codes provided by TA.☆20Jun 3, 2023Updated 2 years ago
- Interface Protocol in Verilog☆51Aug 2, 2019Updated 6 years ago
- Implementation of RISC-V RV32I☆28Aug 30, 2022Updated 3 years ago
- Simple 8-bit UART realization on Verilog HDL.☆115Apr 27, 2024Updated last year
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆121Dec 17, 2023Updated 2 years ago