A Verilog based 5-stage fully functional pipelined RISC-V Processor code.
☆67May 8, 2021Updated 5 years ago
Alternatives and similar repositories for RISC-V-Pipelined-Processor
Users that are interested in RISC-V-Pipelined-Processor are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A verilog based 5-stage pipelined RISC-V Processor code.☆37Mar 25, 2020Updated 6 years ago
- 32-bit 5-stage pipelined RISC-V processor in SystemVerilog☆36Oct 29, 2023Updated 2 years ago
- Implementation of 5 Stage 32I RISC V Pipeline Processor.☆26Sep 6, 2024Updated last year
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆62Jul 5, 2024Updated last year
- APB Timer Unit☆14Oct 30, 2025Updated 6 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A Single Cycle Risc-V 32 bit CPU☆71Jan 14, 2026Updated 3 months ago
- This repository contains the design files of RISC-V Pipeline Core☆71May 11, 2023Updated 3 years ago
- This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog☆29Feb 19, 2025Updated last year
- 32 bit RISC-V CPU implementation in Verilog☆34Feb 9, 2022Updated 4 years ago
- DMA Project using Verilog HDL☆14Dec 26, 2019Updated 6 years ago
- ☆14Sep 27, 2022Updated 3 years ago
- APB master and slave developed in RTL.☆24Oct 25, 2025Updated 6 months ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆26Jul 23, 2023Updated 2 years ago
- Verification IP for Watchdog☆13Apr 6, 2021Updated 5 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆11Mar 12, 2024Updated 2 years ago
- Minimalistic RV32I RISC-V Processor in System Verilog☆28Sep 19, 2023Updated 2 years ago
- Single-Cycle RISC-V Processor in systemverylog☆25Apr 23, 2019Updated 7 years ago
- Tests for the design flow with Synopsys tools for the implementation of a RISC-V processor.☆27Sep 8, 2024Updated last year
- APB VIP (UVM)☆18Sep 6, 2018Updated 7 years ago
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆15Mar 30, 2022Updated 4 years ago
- System Verilog using Functional Verification☆12Apr 8, 2024Updated 2 years ago
- Implementing a five-stage pipeline RSIC-V architecture (RV32I Core instruction set) using Verilog HDL. All the functional modules require…☆36Aug 12, 2020Updated 5 years ago
- Basic RISC-V Test SoC☆191Apr 7, 2019Updated 7 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆56Nov 16, 2023Updated 2 years ago
- The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …☆18Jun 24, 2021Updated 4 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆132Jul 11, 2025Updated 10 months ago
- This repository contains the design files of RISC-V Single Cycle Core☆81Dec 14, 2023Updated 2 years ago
- ☆24Apr 17, 2026Updated 3 weeks ago
- To design test bench of the APB protocol☆20Dec 30, 2020Updated 5 years ago
- ☆17Feb 16, 2023Updated 3 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆19Sep 2, 2023Updated 2 years ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆28Oct 31, 2021Updated 4 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- AXI4 with a FIFO integrated with VIP☆24Feb 29, 2024Updated 2 years ago
- Single Cycle Processor written in SystemVerilog for executing machine code of RISC-V ISA☆29Apr 23, 2023Updated 3 years ago
- UART implementation using verilog☆37Feb 14, 2023Updated 3 years ago
- ☆103Mar 5, 2026Updated 2 months ago
- 5 Day TCL begginer to advanced training workshop by VSD☆19Oct 18, 2023Updated 2 years ago
- RTL Design and Verification☆21Jan 4, 2021Updated 5 years ago
- Architectural design of data router in verilog☆33Dec 29, 2019Updated 6 years ago