EngAhmed21 / RISC-V-Processor-with-Pipelining

Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and multi cycle instructions, ALU unit works in parallel with a multiplication unit, and Reorder Buffer to guarantee in-order termination.
14Updated last year

Alternatives and similar repositories for RISC-V-Processor-with-Pipelining:

Users that are interested in RISC-V-Processor-with-Pipelining are comparing it to the libraries listed below