EngAhmed21 / RISC-V-Processor-with-Pipelining
Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and multi cycle instructions, ALU unit works in parallel with a multiplication unit, and Reorder Buffer to guarantee in-order termination.
☆14Updated last year
Alternatives and similar repositories for RISC-V-Processor-with-Pipelining:
Users that are interested in RISC-V-Processor-with-Pipelining are comparing it to the libraries listed below
- Design and UVM-TB of RISC -V Microprocessor☆17Updated 9 months ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆11Updated 4 years ago
- ☆17Updated 2 years ago
- ☆19Updated 2 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆14Updated last year
- RTL Design and Verification☆13Updated 4 years ago
- ☆12Updated last week
- IEEE Executive project for the year 2021-2022☆9Updated 2 years ago
- CORE-V MCU UVM Environment and Test Bench☆21Updated 8 months ago
- System Verilog using Functional Verification☆10Updated last year
- To design test bench of the APB protocol☆17Updated 4 years ago
- SystemVerilog examples and projects☆17Updated 6 years ago
- This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog☆12Updated last month
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆23Updated last year
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆14Updated 2 years ago
- Asynchronous fifo in verilog☆33Updated 9 years ago
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆25Updated last year
- ☆17Updated 10 years ago
- DMA Hardware Description with Verilog☆13Updated 5 years ago
- verification of simple axi-based cache☆18Updated 5 years ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆19Updated 2 months ago
- Maven Silicon Project☆17Updated 6 years ago
- UVM Testbench for synchronus fifo☆16Updated 4 years ago
- The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …☆17Updated 3 years ago
- ☆13Updated 2 years ago
- Various low power labs using sky130☆12Updated 3 years ago
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆16Updated 11 months ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago