EngAhmed21 / RISC-V-Processor-with-PipeliningLinks
Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and multi cycle instructions, ALU unit works in parallel with a multiplication unit, and Reorder Buffer to guarantee in-order termination.
☆14Updated last year
Alternatives and similar repositories for RISC-V-Processor-with-Pipelining
Users that are interested in RISC-V-Processor-with-Pipelining are comparing it to the libraries listed below
Sorting:
- Design and UVM-TB of RISC -V Microprocessor☆23Updated last year
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆11Updated 11 months ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆13Updated 2 years ago
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆14Updated 4 months ago
- ☆14Updated 2 years ago
- CORE-V MCU UVM Environment and Test Bench☆21Updated last year
- General Purpose AXI Direct Memory Access☆57Updated last year
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆13Updated 2 years ago
- SoC Based on ARM Cortex-M3☆32Updated 2 months ago
- Andes Vector Extension support added to riscv-dv☆17Updated 5 years ago
- RTL code of some arbitration algorithm☆14Updated 5 years ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- ☆20Updated 2 years ago
- ☆34Updated 6 years ago
- UVM Testbench for synchronus fifo☆17Updated 4 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆12Updated 5 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆44Updated last year
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆35Updated 2 years ago
- Two Level Cache Controller implementation in Verilog HDL☆51Updated 5 years ago
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆22Updated 6 months ago
- To design test bench of the APB protocol☆17Updated 4 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- Implementation of the PCIe physical layer☆47Updated 3 weeks ago
- 128KB AXI cache (32-bit in, 256-bit out)☆51Updated 4 years ago
- ☆17Updated 10 years ago
- Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM☆35Updated 3 weeks ago
- ☆30Updated 2 weeks ago
- ☆29Updated 4 years ago
- Various low power labs using sky130☆11Updated 3 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆20Updated 11 months ago