Alternatives and similar repositories for tinyrv:

Users that are interested in tinyrv are comparing it to the libraries listed below

• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆92Updated last month
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆112Updated last week
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆69Updated 11 months ago
• riscv-software-src / riscof
  ☆77Updated 3 weeks ago
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆30Updated 11 months ago
• stnolting / riscv-gcc-prebuilt
  📦 Prebuilt RISC-V GCC toolchains for x64 Linux.
  ☆101Updated last month
• cr1901 / sentinel
  Another size-optimized RISC-V CPU for your consideration.
  ☆58Updated 2 weeks ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆90Updated 7 months ago
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆32Updated this week
• chili-chips-ba / openCologne
  Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…
  ☆61Updated this week
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆80Updated 6 months ago
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆55Updated last year
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆144Updated 5 months ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆96Updated 3 years ago
• aignacio / nox
  RISC-V Nox core
  ☆62Updated 3 weeks ago
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆61Updated 10 months ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆80Updated this week
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆91Updated 2 weeks ago
• lowRISC / muntjac
  64-bit multicore Linux-capable RISC-V processor
  ☆89Updated 7 months ago
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆150Updated this week
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆89Updated 2 weeks ago
• stnolting / neorv32-setups
  📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
  ☆75Updated this week
• riscvarchive / riscv-aclint
  ☆42Updated 3 years ago
• tomverbeure / gdbwave
  GDB server to debug CPU simulation waveform traces
  ☆44Updated 3 years ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆131Updated this week
• rsnikhil / Learn_Bluespec_and_RISCV_Design
  Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)
  ☆71Updated 7 months ago
• ChrisPVille / jtaglet
  Easy-to-use JTAG TAP and Debug Controller core written in Verilog
  ☆28Updated 6 years ago
• SpinalHDL / openocd_riscv
  Spen's Official OpenOCD Mirror
  ☆48Updated last month
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆50Updated 2 months ago
• riscv / riscv-cheri
  This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory prot…
  ☆65Updated this week