Alternatives and similar repositories for tinyrv

Users that are interested in tinyrv are comparing it to the libraries listed below

• riscv-software-src / riscof
  ☆85Updated 4 months ago
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆167Updated 2 weeks ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆117Updated last month
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆402Updated last week
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆101Updated 3 years ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆265Updated 3 months ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆147Updated 9 months ago
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆244Updated 10 months ago
• SpinalHDL / NaxRiscv
  ☆293Updated last month
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆241Updated 9 months ago
• bsc-loca / sargantana
  ☆105Updated this week
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆126Updated last week
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆159Updated 4 months ago
• pulp-platform / bender
  A dependency management tool for hardware projects.
  ☆314Updated 2 weeks ago
• olofk / corescore
  CoreScore
  ☆160Updated 6 months ago
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆226Updated last year
• riscv / riscv-plic-spec
  PLIC Specification
  ☆144Updated last week
• zephray / RISu064
  Dual-issue RV64IM processor for fun & learning
  ☆63Updated 2 years ago
• kuznia-rdzeni / coreblocks
  RISC-V out-of-order core for education and research purposes
  ☆60Updated last week
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆218Updated 2 months ago
• fusesoc / blinky
  Example LED blinking project for your FPGA dev board of choice
  ☆179Updated 2 months ago
• stnolting / riscv-gcc-prebuilt
  📦 Prebuilt RISC-V GCC toolchains for x64 Linux.
  ☆104Updated 5 months ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆123Updated 6 years ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆229Updated 8 months ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆85Updated 3 weeks ago
• regymm / quasiSoC
  Linux capable RISC-V SoC designed to be readable and useful.
  ☆151Updated 2 months ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆105Updated this week
• riscv-ovpsim / imperas-riscv-tests
  ☆182Updated last year
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆92Updated 9 months ago
• lowRISC / muntjac
  64-bit multicore Linux-capable RISC-V processor
  ☆95Updated 3 months ago