vinayrayapati / rv32i
Implementation of RISC-V RV32I
☆13Updated 2 years ago
Related projects ⓘ
Alternatives and complementary repositories for rv32i
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆21Updated last year
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆27Updated 2 years ago
- AXI4 and AXI4-Lite interface definitions☆83Updated 4 years ago
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆32Updated 4 months ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆50Updated 2 years ago
- 5 Day TCL begginer to advanced training workshop by VSD☆16Updated last year
- An AXI4 crossbar implementation in SystemVerilog☆123Updated last week
- Architectural design of data router in verilog☆27Updated 4 years ago
- Two Level Cache Controller implementation in Verilog HDL☆36Updated 4 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆49Updated 2 years ago
- This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…☆17Updated last year
- This is full tutorial of UVM (Universal Verification Methodology) for a simple ALU unit☆18Updated 6 years ago
- A Fast, Low-Overhead On-chip Network☆137Updated 3 weeks ago
- AXI DMA 32 / 64 bits☆100Updated 10 years ago
- ☆15Updated last year
- 2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…☆9Updated 7 months ago
- ☆13Updated 8 months ago
- VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.☆15Updated 6 months ago
- ☆12Updated 9 months ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆52Updated last year
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆53Updated 2 weeks ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆68Updated 11 months ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆96Updated 9 months ago
- DDR2 memory controller written in Verilog☆72Updated 12 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆68Updated 6 years ago
- Verilog Configurable Cache☆167Updated 2 months ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆146Updated this week
- ☆13Updated 2 years ago
- ☆36Updated 3 years ago