cepdnaclk / e16-co502-RV32IM-pipeline-implementation-group1Links
The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pipeline CPU supports the entire RV32IM ISA which contains 45 instructions. The designed pipeline CPU was implemented using behavioral modeling in verilogHDL and icarus Verilog was used compile and simulate. gtkWa…
☆26Updated 4 years ago
Alternatives and similar repositories for e16-co502-RV32IM-pipeline-implementation-group1
Users that are interested in e16-co502-RV32IM-pipeline-implementation-group1 are comparing it to the libraries listed below
Sorting:
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆26Updated 2 years ago
- ☆17Updated 2 years ago
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆55Updated last year
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆118Updated 2 years ago
- Two Level Cache Controller implementation in Verilog HDL☆53Updated 5 years ago
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆17Updated 2 years ago
- 5 Day TCL begginer to advanced training workshop by VSD☆18Updated 2 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆49Updated 3 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆81Updated 4 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆103Updated 2 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆29Updated 3 years ago
- A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.☆39Updated 3 months ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆37Updated 3 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆33Updated 4 years ago
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆44Updated 3 years ago
- Design Verification Engineer interview preparation guide.☆41Updated 5 months ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆98Updated last year
- ☆14Updated 3 years ago
- Implementing Different Adder Structures in Verilog☆76Updated 6 years ago
- Introductory course into static timing analysis (STA).☆99Updated 5 months ago
- General Purpose AXI Direct Memory Access☆62Updated last year
- ☆15Updated 2 years ago
- Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Syno…☆13Updated 4 years ago
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆15Updated last year
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆130Updated 2 months ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆64Updated last year
- Complete tutorial code.☆22Updated last year
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆67Updated 3 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆48Updated 2 years ago
- 2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…☆30Updated last year