Implementation of 5 Stage 32I RISC V Pipeline Processor.
☆25Sep 6, 2024Updated last year
Alternatives and similar repositories for RISC-V-32I-5-stage-Pipeline-Core
Users that are interested in RISC-V-32I-5-stage-Pipeline-Core are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 32-bit 5-stage pipelined RISC-V processor in SystemVerilog☆36Oct 29, 2023Updated 2 years ago
- This repository contains the design files of RISC-V Pipeline Core☆71May 11, 2023Updated 2 years ago
- ESP32 esp-idf MPU6050 component☆11Mar 28, 2022Updated 4 years ago
- A Verilog based 5-stage fully functional pipelined RISC-V Processor code.☆67May 8, 2021Updated 4 years ago
- verilog实现systolic array及配套IO☆12Dec 2, 2024Updated last year
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- This repository implements a scaled-down LLaMA 2-like model on an ARM Cortex-M3 soft core, with a custom systolic array RTL module for ef…☆13Jun 25, 2025Updated 10 months ago
- Radix-4 1024 point fft in verilog☆12Apr 29, 2020Updated 6 years ago
- ☆15Sep 27, 2022Updated 3 years ago
- This repository contains the tasks performed for VL508- Physical Design of ASIC Course (Fall 2024)☆33Nov 25, 2024Updated last year
- C++17 Neural Network (NN), Convolutional Neural Network (CNN) and Deep Learning for Esp32 on IDF from scratch☆23Aug 23, 2023Updated 2 years ago
- Some test files for STM32 series of processors☆25Feb 11, 2026Updated 2 months ago
- ☆35Apr 20, 2021Updated 5 years ago
- Blocks & Bots: An Open Chip Playground augmented with LLMs. Please check: https://sscs.ieee.org/technical-committees/tc-ose/sscs-pico-des…☆76Dec 16, 2025Updated 4 months ago
- UART implementation using verilog☆36Feb 14, 2023Updated 3 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- 256-bit vector processor based on the RISC-V vector (V) extension☆33May 1, 2021Updated 5 years ago
- Extension giúp ta tự động điền form Quy chế + Pháp Luật - HUST☆21Apr 19, 2026Updated 2 weeks ago
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆47Jan 26, 2023Updated 3 years ago
- Real-time streaming of OV7670 camera via VGA with a 640x480 resolution at 30fps☆77Nov 15, 2021Updated 4 years ago
- An Arduino and IMU-based virtual drum kit played via 3D motion tracking and Python audio playback.☆48Mar 1, 2026Updated 2 months ago
- ESP32-BONGO-CAT☆39Jun 26, 2024Updated last year
- Code repo for https://armasm.com☆45Jan 11, 2024Updated 2 years ago
- Source code of the PPoPP '22 paper: "TileSpGEMM: A Tiled Algorithm for Parallel Sparse General Matrix-Matrix Multiplication on GPUs" by Y…☆46May 22, 2024Updated last year
- This repository contains the design files of RISC-V Single Cycle Core☆81Dec 14, 2023Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Verilog Implementation of 32-bit Floating Point Adder☆48May 4, 2020Updated 5 years ago
- This is a verilog implementation of 4x4 systolic array multiplier☆82Nov 2, 2020Updated 5 years ago
- A project dedicated to developing a hardware Integrated Circuit (IC) for a Spike Neural Network (SNN), powered by the RTL code generated …☆69Feb 18, 2024Updated 2 years ago
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆121Nov 10, 2025Updated 5 months ago
- Here are my solutions to HDLbits Verilog problem sets (HDLbits: https://hdlbits.01xz.net/wiki/Main_Page).☆94Sep 20, 2023Updated 2 years ago
- ☆194Updated this week
- RTL implementation of Flex-DPE.☆116Feb 22, 2020Updated 6 years ago
- Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in …☆148Jul 17, 2022Updated 3 years ago
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆148Dec 2, 2019Updated 6 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Basic RISC-V Test SoC☆189Apr 7, 2019Updated 7 years ago
- LoRa device driver as a kernel module☆143Jun 4, 2019Updated 6 years ago
- Pico controller for Chunithm-type rhythm game☆169Apr 19, 2026Updated 2 weeks ago
- Flash-LLM: Enabling Cost-Effective and Highly-Efficient Large Generative Model Inference with Unstructured Sparsity☆243Sep 24, 2023Updated 2 years ago
- My coursework for Machine Learning (2021 Spring) at National Taiwan University (NTU)☆170Feb 19, 2022Updated 4 years ago
- 《C++ Primer 中文版（第 5 版）》学习仓库，包括笔记和课后练习答案。☆228Apr 7, 2023Updated 3 years ago
- NCTU 2021 Spring Integrated Circuit Design Laboratory☆203Apr 2, 2023Updated 3 years ago