This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other details
☆49Mar 22, 2019Updated 7 years ago
Alternatives and similar repositories for VLSI-Design-Digital-System
Users that are interested in VLSI-Design-Digital-System are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Schematic, Layout Design & Simulation in 180nm Technology☆23Nov 21, 2020Updated 5 years ago
- RTL Synthesis for Fast Arithmetic circuits like Booth encoded Multipliers, Carry Save Adders, Fixed-Point and Floating-Point conversions,…☆22Nov 26, 2018Updated 7 years ago
- The Repository contains the code of various Digital Circuits☆13Aug 7, 2023Updated 3 years ago
- A Spiking Neuron Network Project in Verilog Implementation☆28Apr 5, 2018Updated 8 years ago
- EE 272B - VLSI Design Project☆15Jun 24, 2021Updated 5 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…☆32Jun 4, 2024Updated 2 years ago
- This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specificatio…☆38Jan 23, 2024Updated 2 years ago
- A simple tool to demonstrate the physical design steps of VLSI Design Flow.☆11Dec 13, 2020Updated 5 years ago
- This project offers an immersive tutorial experienced within the context of the Advanced Physical Design, focusing on the utilization of …☆41Sep 21, 2023Updated 2 years ago
- Programming assignments for Coursera's U of I VLSI CAD: Logic to Layout☆14May 11, 2014Updated 12 years ago
- Semiconductor Packaging Fundamentals☆38May 19, 2025Updated last year
- This project is about building a high FOM 2.4 GHz LNA for Bluetooth Low-Energy (BLE) Standards, using 45nm CMOS technology.☆17Mar 17, 2019Updated 7 years ago
- Открытое RISC-V процессорное ядро MIRISCV для образовательных целей☆32Dec 5, 2024Updated last year
- Education kit for teaching VLSI fundamentals through practical microprocessor design using industry EDA tools (educational)☆355May 30, 2025Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆10Aug 30, 2024Updated 2 years ago
- An interactive digital logic simulator with verilog support (Yosys)☆29Apr 2, 2026Updated 5 months ago
- The project involves the design of a 4X4 (16-bit) SRAM Memory Array using Cadence Virtuoso☆68Mar 21, 2024Updated 2 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆128Jul 9, 2023Updated 3 years ago
- Courseworks of CS6165 VLSI Physical Design Automation, NTHU.☆49Jan 23, 2021Updated 5 years ago
- ☆17Jul 14, 2024Updated 2 years ago
- This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, …☆40Apr 7, 2019Updated 7 years ago
- All the projects and assignments done as part of VLSI course.☆21Sep 23, 2020Updated 5 years ago
- ☆16Jun 28, 2021Updated 5 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Time to Digital Converter (TDC)☆38Dec 27, 2020Updated 5 years ago
- The template for VLSI project☆27May 10, 2019Updated 7 years ago
- Implementing Different Adder Structures in Verilog☆77Sep 3, 2019Updated 7 years ago
- A dec-bin converter uses 2's complement.☆10Sep 24, 2024Updated last year
- Open Source VLSI Tools☆33Feb 6, 2021Updated 5 years ago
- Tiny Tapeout GDS Action (using LibreLane)☆26Jul 30, 2026Updated last month
- Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.☆41May 10, 2019Updated 7 years ago
- Interchange formats for chip design.☆40Feb 15, 2026Updated 6 months ago
- ☆15Jun 17, 2025Updated last year
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Verilog HDL implementation of SDRAM controller and SDRAM model☆49Jun 19, 2024Updated 2 years ago
- This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.☆45Mar 2, 2022Updated 4 years ago
- Fundamental analog circuit designs to kick start and embark the journey in the world of IC design.☆35Aug 31, 2023Updated 3 years ago
- A modular hardware abstraction library☆53Aug 3, 2026Updated last month
- UART implementation using verilog☆39Feb 14, 2023Updated 3 years ago
- helping first timers learn opensource contributions!☆32Aug 8, 2025Updated last year
- 🤖 An automated NTU Thesis LaTeX continuous integration and continuous deploying service built up with GitHub Actions.☆10May 8, 2020Updated 6 years ago