mihir8181 / VLSI-Design-Digital-SystemLinks
This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other details
☆28Updated 6 years ago
Alternatives and similar repositories for VLSI-Design-Digital-System
Users that are interested in VLSI-Design-Digital-System are comparing it to the libraries listed below
Sorting:
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆46Updated 4 years ago
- Repository for system verilog labs from cadence☆13Updated 5 years ago
- This repository contains the design files of RISC-V Single Cycle Core☆51Updated last year
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆43Updated 3 years ago
- Physical Design Flow from RTL to GDS using Opensource tools.☆106Updated 4 years ago
- RISC-V Embedded Processor for Approximate Computing☆126Updated last month
- This repository in a walk through the entire process of PLL IC designing from the tools to the final tapeout.☆20Updated 3 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆99Updated last year
- ☆15Updated 2 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆64Updated 5 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆102Updated 2 months ago
- This repository contains the design files of RISC-V Pipeline Core☆49Updated 2 years ago
- Simple 8-bit UART realization on Verilog HDL.☆107Updated last year
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆30Updated 4 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆71Updated 2 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆83Updated 2 years ago
- A simple implementation of a UART modem in Verilog.☆142Updated 3 years ago
- IP operations in verilog (simulation and implementation on ice40)☆56Updated 5 years ago
- ☆27Updated last week
- A Verilog based 5-stage fully functional pipelined RISC-V Processor code.☆43Updated 4 years ago
- ☆95Updated last year
- Schematic, Layout Design & Simulation in 180nm Technology☆21Updated 4 years ago
- Implementing Different Adder Structures in Verilog☆70Updated 5 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆65Updated 2 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆66Updated last year
- Basic RISC-V Test SoC☆137Updated 6 years ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆78Updated last year
- DMA Hardware Description with Verilog☆14Updated 5 years ago