This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other details
☆47Mar 22, 2019Updated 7 years ago
Alternatives and similar repositories for VLSI-Design-Digital-System
Users that are interested in VLSI-Design-Digital-System are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Schematic, Layout Design & Simulation in 180nm Technology☆23Nov 21, 2020Updated 5 years ago
- RTL Synthesis for Fast Arithmetic circuits like Booth encoded Multipliers, Carry Save Adders, Fixed-Point and Floating-Point conversions,…☆21Nov 26, 2018Updated 7 years ago
- The Repository contains the code of various Digital Circuits☆13Aug 7, 2023Updated 2 years ago
- A Spiking Neuron Network Project in Verilog Implementation☆27Apr 5, 2018Updated 8 years ago
- EE 272B - VLSI Design Project☆15Jun 24, 2021Updated 5 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…☆29Jun 4, 2024Updated 2 years ago
- This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specificatio…☆36Jan 23, 2024Updated 2 years ago
- This project shows how to model a 4-bit flash ADC and a 4-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs …☆21Apr 20, 2019Updated 7 years ago
- A simple tool to demonstrate the physical design steps of VLSI Design Flow.☆11Dec 13, 2020Updated 5 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆60Jul 9, 2021Updated 5 years ago
- Programming assignments for Coursera's U of I VLSI CAD: Logic to Layout☆14May 11, 2014Updated 12 years ago
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆91Mar 19, 2026Updated 4 months ago
- Semiconductor Packaging Fundamentals☆36May 19, 2025Updated last year
- This project is about building a high FOM 2.4 GHz LNA for Bluetooth Low-Energy (BLE) Standards, using 45nm CMOS technology.☆16Mar 17, 2019Updated 7 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Открытое RISC-V процессорное ядро MIRISCV для образовательных целей☆31Dec 5, 2024Updated last year
- Education kit for teaching VLSI fundamentals through practical microprocessor design using industry EDA tools (educational)☆344May 30, 2025Updated last year
- ☆10Aug 30, 2024Updated last year
- An interactive digital logic simulator with verilog support (Yosys)☆28Apr 2, 2026Updated 3 months ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆123Jul 9, 2023Updated 3 years ago
- Courseworks of CS6165 VLSI Physical Design Automation, NTHU.☆49Jan 23, 2021Updated 5 years ago
- RTL to GDS via Cadence Tools☆19May 17, 2022Updated 4 years ago
- FPGA based MIDI keyboard project for EEE 304 (Digital Electronics Laboratory)☆14Sep 21, 2022Updated 3 years ago
- ☆16Jul 14, 2024Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, …☆40Apr 7, 2019Updated 7 years ago
- All the projects and assignments done as part of VLSI course.☆20Sep 23, 2020Updated 5 years ago
- ☆15Jun 28, 2021Updated 5 years ago
- Time to Digital Converter (TDC)☆37Dec 27, 2020Updated 5 years ago
- The template for VLSI project☆27May 10, 2019Updated 7 years ago
- Implementing Different Adder Structures in Verilog☆77Sep 3, 2019Updated 6 years ago
- A dec-bin converter uses 2's complement.☆10Sep 24, 2024Updated last year
- Open Source VLSI Tools☆33Feb 6, 2021Updated 5 years ago
- A WIP library to control B1500 and similar testers via the VISA protocol, built on pyvisa☆11Nov 4, 2016Updated 9 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Tiny Tapeout GDS Action (using LibreLane)☆24Jul 19, 2026Updated last week
- Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.☆41May 10, 2019Updated 7 years ago
- The OggBox project - an open hardware portable music player based on STM32 and VLSI parts☆16Oct 11, 2019Updated 6 years ago
- Interchange formats for chip design.☆39Feb 15, 2026Updated 5 months ago
- ☆15Jun 17, 2025Updated last year
- Verilog HDL implementation of SDRAM controller and SDRAM model☆46Jun 19, 2024Updated 2 years ago
- This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.☆44Mar 2, 2022Updated 4 years ago