Alternatives and similar repositories for PCIE_AXI_BRIDGE

Users that are interested in PCIE_AXI_BRIDGE are comparing it to the libraries listed below

• muzafferkal / axi-bfm
  AXI3 Bus Functional Models (Initiator & Target)
  ☆30Updated 3 years ago
• freecores / axi_master
  Generic AXI master stub
  ☆19Updated 11 years ago
• Elphel / eddr3
  mirror of https://git.elphel.com/Elphel/eddr3
  ☆41Updated 8 years ago
• fpgasystems / groundhog
  Groundhog - Serial ATA Host Bus Adapter
  ☆24Updated 7 years ago
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆41Updated 4 years ago
• pulp-platform / axi2apb
  ☆21Updated 5 years ago
• efabless / raptor_soc_template
  Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.
  ☆22Updated 6 years ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆34Updated 11 months ago
• JakeMercer / mac
  An Ethernet MAC conforming to IEEE 802.3
  ☆23Updated 8 years ago
• ZipCPU / axidmacheck
  AXI DMA Check: A utility to measure DMA speeds in simulation
  ☆15Updated 11 months ago
• CospanDesign / verilog_ppfifo_demo
  Simple demo showing how to use the ping pong FIFO
  ☆16Updated 9 years ago
• pulp-platform / axi_spi_slave
  ☆28Updated 4 years ago
• pulp-platform / axi_spi_master
  ☆22Updated 6 years ago
• freecores / wb_dma
  WISHBONE DMA/Bridge IP Core
  ☆18Updated 11 years ago
• open-dv / dma_axi
  ☆16Updated 6 years ago
• CospanDesign / vivado-ip-cores
  IP Cores that can be used within Vivado
  ☆27Updated 4 years ago
• www-asics-ws / wb_conmax
  WISHBONE Interconnect
  ☆11Updated 8 years ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆20Updated 2 years ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆31Updated 7 years ago
• iammituraj / fifo
  Synchronous FIFOs designed in Verilog/System Verilog.
  ☆24Updated 3 weeks ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆61Updated 5 years ago
• iammituraj / skid_buffer
  Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.
  ☆27Updated 2 months ago
• Cognoscan / AxiCores
  AXI4-Compatible Verilog Cores, along with some helper modules.
  ☆17Updated 5 years ago
• KutuSystems / XilinxIP
  Xilinx IP repository
  ☆13Updated 7 years ago
• AugustinJose1221 / FFTx32
  A 32 point radix-2 FFT module written in Verilog
  ☆25Updated 5 years ago
• freecores / pipelined_fft_64
  Pipelined FFT/IFFT 64 points processor
  ☆11Updated 11 years ago
• freecores / video_stream_scaler
  Video Stream Scaler
  ☆40Updated 11 years ago
• jdocampom / JPEG-Decoder
  Verilog Code for a JPEG Decoder
  ☆34Updated 7 years ago
• hellgate202 / crc_calc
  Simple and effective parallel CRC calculator written in synthesizable SystemVerilog
  ☆15Updated 6 years ago
• DUNE / pl-nvme
  ☆36Updated 5 years ago