saunak1994 / CyNAPSEv11
The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL
☆33Updated 5 years ago
Alternatives and similar repositories for CyNAPSEv11
Users that are interested in CyNAPSEv11 are comparing it to the libraries listed below
Sorting:
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆36Updated 5 years ago
- ☆18Updated 4 years ago
- CORDIC-SNN, followed with "Unsupervised learning of digital recognition using STDP" published in 2015, frontiers☆23Updated 5 years ago
- ☆17Updated 4 years ago
- HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx…☆58Updated 2 months ago
- This is the RTL implementation of Shenjing, a low power neuromorphic computing accelerator☆17Updated 5 years ago
- The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…☆11Updated 2 years ago
- A Spiking Neuron Network Project in Verilog Implementation☆22Updated 7 years ago
- tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.☆56Updated 2 years ago
- IEEE Transactions on Circuits and Systems I: Efficient FPGA Implementations of Pair and Triplet-based STDP for Neuromorphic Architectures☆26Updated 5 years ago
- Spiking Neural Network RTL Implementation☆57Updated 3 years ago
- [FPL 2021] SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs.☆55Updated 3 years ago
- A repository FPGA-friendly SNN models☆34Updated 4 years ago
- FPGA acceleration of a Spike-Timing-Dependent Plasticity learning algorithm for Spiking Neural Networks☆35Updated 4 years ago
- Framework for radix encoded SNN on FPGA☆12Updated 3 years ago
- A three-layer LIF neuron SNN accelerator. The first layer is the input layer and has 784 neurons, that receive the encoded spikes. The se…☆12Updated last year
- Spiking Neural Network Accelerator☆15Updated 2 years ago
- This project aims to develop a novel neuromorphic NoC architecture based on RISC-V ISA to support spiking neural network applications, an…☆21Updated last year
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)☆48Updated 3 years ago
- Spiking neural network for Zynq devices with Vivado HLS☆33Updated 7 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- ☆24Updated 2 years ago
- Spiking neural network implementation using Verilog with LIF (Leaky Integrate-and-Fire) neurons☆16Updated 4 years ago
- ☆46Updated last year
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- Code for the ISCAS23 paper "The Hardware Impact of Quantization and Pruning for Weights in Spiking Neural Networks"☆11Updated 2 years ago
- ReckOn: A Spiking RNN Processor Enabling On-Chip Learning over Second-Long Timescales - HDL source code and documentation.☆84Updated 3 years ago
- Leaky Integrate and Fire (LIF) model implementation for FPGA☆62Updated last year
- Systolic array based simple TPU for CNN on PYNQ-Z2☆31Updated 2 years ago