aignacio / mpsoc_exampleLinks
☆59Updated 3 years ago
Alternatives and similar repositories for mpsoc_example
Users that are interested in mpsoc_example are comparing it to the libraries listed below
Sorting:
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆50Updated 9 months ago
- Hamming ECC Encoder and Decoder to protect memories☆33Updated 6 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated last month
- A collection of debugging busses developed and presented at zipcpu.com☆41Updated last year
- Mathematical Functions in Verilog☆93Updated 4 years ago
- Bitstream relocation and manipulation tool.☆47Updated 2 years ago
- RISC-V Nox core☆66Updated 2 weeks ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆35Updated last week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆117Updated 3 weeks ago
- Demo SoC for SiliconCompiler.☆60Updated 2 months ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆66Updated 5 months ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆47Updated last year
- Xilinx Unisim Library in Verilog☆81Updated 5 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆68Updated 7 months ago
- RISCV model for Verilator/FPGA targets☆53Updated 5 years ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆28Updated last year
- Wishbone interconnect utilities☆41Updated 5 months ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆45Updated 3 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- pulp_soc is the core building component of PULP based SoCs☆80Updated 4 months ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆98Updated 2 weeks ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆106Updated 4 years ago
- ☆33Updated 2 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆75Updated 2 years ago
- A simple DDR3 memory controller☆58Updated 2 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆93Updated this week
- JTAG DPI module for SystemVerilog RTL simulations☆28Updated 9 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆115Updated last year
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆63Updated 6 months ago
- ☆39Updated last year