aignacio / mpsoc_example
☆59Updated 3 years ago
Alternatives and similar repositories for mpsoc_example:
Users that are interested in mpsoc_example are comparing it to the libraries listed below
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated 11 months ago
- RISC-V Nox core☆62Updated last month
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆65Updated 4 months ago
- Hamming ECC Encoder and Decoder to protect memories☆32Updated 2 months ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆45Updated 6 months ago
- A simple DDR3 memory controller☆54Updated 2 years ago
- Platform Level Interrupt Controller☆40Updated 11 months ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆68Updated 2 years ago
- Open FPGA Modules☆23Updated 6 months ago
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 5 months ago
- ☆25Updated 3 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆102Updated 3 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆41Updated last year
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆54Updated 3 months ago
- Generic FIFO implementation with optional FWFT☆57Updated 4 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆73Updated 2 years ago
- RISCV model for Verilator/FPGA targets☆51Updated 5 years ago
- ☆55Updated 4 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆61Updated 11 months ago
- pulp_soc is the core building component of PULP based SoCs☆79Updated last month
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 4 years ago
- Bitstream relocation and manipulation tool.☆44Updated 2 years ago
- Open source ISS and logic RISC-V 32 bit project☆51Updated this week
- UART -> AXI Bridge☆61Updated 3 years ago
- ☆26Updated 2 weeks ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆29Updated 4 months ago
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago
- ☆13Updated last month
- ☆33Updated 2 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 3 years ago