Alternatives and similar repositories for mpsoc_example:

Users that are interested in mpsoc_example are comparing it to the libraries listed below

• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 10 months ago
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆44Updated 4 months ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆62Updated 2 months ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆36Updated 10 months ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆65Updated 2 years ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆55Updated 4 years ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆101Updated 3 years ago
• taneroksuz / fpu-sp
  IEEE 754 single precision floating point library in systemverilog and vhdl
  ☆29Updated 2 months ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆62Updated 4 years ago
• aignacio / nox
  RISC-V Nox core
  ☆62Updated 7 months ago
• ultraembedded / core_axi_cache
  128KB AXI cache (32-bit in, 256-bit out)
  ☆48Updated 3 years ago
• olofk / fusesocotb
  Quick'n'dirty FuseSoC+cocotb example
  ☆18Updated 3 months ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆54Updated 2 years ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆75Updated this week
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆43Updated 3 months ago
• openhwgroup / cve2
  The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…
  ☆37Updated this week
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆47Updated last month
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆30Updated last month
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆30Updated 4 months ago
• ucb-cs250 / caravel_fpga250
  FPGA250 aboard the eFabless Caravel
  ☆29Updated 4 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆49Updated 10 months ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆79Updated this week
• CESNET / ofm
  Open FPGA Modules
  ☆23Updated 5 months ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆63Updated last month
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆39Updated last year
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆49Updated last year
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆34Updated 3 years ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆17Updated last year
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆79Updated 2 years ago
• BrianHGinc / BrianHG-DDR3-Controller
  DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…
  ☆75Updated 11 months ago