Alternatives and similar repositories for Stochastic-computing-based-neural-network-accelerator:

Users that are interested in Stochastic-computing-based-neural-network-accelerator are comparing it to the libraries listed below

• saunak1994 / CyNAPSEv11
  The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL
  ☆32Updated 5 years ago
• arkhodamoradi / s2n2
  ☆17Updated 3 years ago
• DanielGerlinghoff / radix-encoding
  Framework for radix encoded SNN on FPGA
  ☆13Updated 3 years ago
• Spiritator / FPGA_LeNet5_ws_8x8
  FPGA implement of 8x8 weight stationary systolic array DNN accelerator
  ☆10Updated 3 years ago
• YulhwaKim / RRAMScalable_BNN
  Neural Network-Hardware Co-design for Scalable RRAM-based BNN Accelerators
  ☆11Updated 5 years ago
• zwhexplorer / Spiking-Neural-Network-Accelerator-EE552-project
  Spiking Neural Network Accelerator
  ☆13Updated 2 years ago
• neurosim / DNN_NeuroSim_V2.0
  Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)
  ☆46Updated 3 years ago
• mustard-seed / SparseDNNAccelerator
  Sparse CNN Accelerator targeting Intel FPGA
  ☆11Updated 3 years ago
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆20Updated 3 years ago
• CASR-HKU / MSD-FCCM23
  Open-source of MSD framework
  ☆16Updated last year
• fffasttime / AnyPackingNet
  ☆25Updated last month
• SivannaKing / SEU-ASIC-IOT-ECGAI
  Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators
  ☆17Updated last year
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 7 years ago
• cornell-zhang / FracBNN
  FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations
  ☆89Updated 3 years ago
• snagiri / CSE237D-PYNQ-SNN-Accelerator
  Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board
  ☆32Updated 5 years ago
• sherylll / lenet5-accelerator
  FPGA and GPU acceleration of LeNet5
  ☆35Updated 5 years ago
• cceroici / Stochastic-Neural-Network
  Fully Hardware-Based Stochastic Neural Network
  ☆19Updated 5 years ago
• hyupupup / conv_systolic_array
  (Verilog) A simple convolution layer implementation with systolic array structure
  ☆12Updated 2 years ago
• BoooC / CNN-Accelerator-Based-on-Eyeriss-v2
  A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network
  ☆39Updated 4 months ago
• xliu0709 / WinoCNN
  An HLS based winograd systolic CNN accelerator
  ☆49Updated 3 years ago
• suchuankai / CNN-hw-accelerator
  CNN hardware accelerator to accelerate quantized LeNet-5 model
  ☆26Updated last year
• ralbertazzi / bnn
  Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools
  ☆47Updated 6 years ago
• pierpaolomori / SemanticSegmentationFPGA
  ☆10Updated 2 years ago
• xliu0709 / DACSDC2021
  ☆11Updated 9 months ago
• adamsolomou / SC-DNN
  Stochastic Computing for Deep Neural Networks
  ☆30Updated 4 years ago
• ryaanluke / DNN-Hardware-Accelerator
  SystemVerilog files for lab project on a DNN hardware accelerator
  ☆13Updated 3 years ago
• wzc810049078 / systolic-array-matrix-multiplier
  A systolic array matrix multiplier
  ☆24Updated 5 years ago
• jgoeders / dac_sdc_2020_designs
  Designs for finalist teams of the DAC System Design Contest
  ☆36Updated 4 years ago
• CASR-HKU / DPACS
  ☆18Updated last year
• hazooree / LeNet-CNN-Accelerator-Hardware-for-FPGA
  An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017
  ☆14Updated 5 years ago