sweetwenwen / Stochastic-computing-based-neural-network-acceleratorLinks
☆11Updated 6 years ago
Alternatives and similar repositories for Stochastic-computing-based-neural-network-accelerator
Users that are interested in Stochastic-computing-based-neural-network-accelerator are comparing it to the libraries listed below
Sorting:
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆38Updated 6 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆16Updated 4 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆95Updated 4 years ago
- bitfusion verilog implementation☆12Updated 3 years ago
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆36Updated 6 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)☆53Updated 4 years ago
- Stochastic Computing for Deep Neural Networks☆33Updated 5 years ago
- ☆10Updated last year
- HLS implemented systolic array structure☆41Updated 8 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆22Updated 4 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆18Updated last year
- Quantized Training for Convolutional Neural Networks using Xilinx Brevitas☆12Updated 3 years ago
- Fully Hardware-Based Stochastic Neural Network☆22Updated 10 months ago
- A collection of tutorials for the fpgaConvNet framework.☆47Updated last year
- ☆18Updated 2 years ago
- Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators☆16Updated 2 years ago
- ☆18Updated last year
- Collection of kernel accelerators optimised for LLM execution☆25Updated 3 weeks ago
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- Framework for radix encoded SNN on FPGA☆18Updated 4 years ago
- Open-source of MSD framework☆16Updated 2 years ago
- FPGA and GPU acceleration of LeNet5☆34Updated 6 years ago
- A systolic array matrix multiplier☆29Updated 6 years ago
- Sparse CNN Accelerator targeting Intel FPGA☆12Updated 4 years ago
- ☆17Updated 4 years ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆20Updated 6 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆83Updated 4 years ago
- Spiking Neural Network Accelerator☆15Updated 3 years ago
- CNN Accelerator in Frequency Domain☆12Updated 5 years ago
- Neural Network-Hardware Co-design for Scalable RRAM-based BNN Accelerators☆11Updated 6 years ago