Ratatoskr NoC Simulator
☆29Apr 13, 2021Updated 5 years ago
Alternatives and similar repositories for ratatoskr
Users that are interested in ratatoskr are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Extending BookSim2.0 and HotSpot6.0 for Power, Performance and Thermal evaluation of 3D NoC Architectures☆14Aug 9, 2019Updated 6 years ago
- Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.☆25Nov 2, 2015Updated 10 years ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Feb 12, 2019Updated 7 years ago
- SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).☆14Apr 20, 2014Updated 12 years ago
- A configurable general purpose graphics processing unit for☆12May 18, 2019Updated 6 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- ☆62Jun 3, 2025Updated 11 months ago
- gem5-X open source project☆18Mar 28, 2023Updated 3 years ago
- ☆19Feb 18, 2021Updated 5 years ago
- Accelerate multihead attention transformer model using HLS for FPGA☆12Dec 7, 2023Updated 2 years ago
- cycle accurate Network-on-Chip Simulator☆35Jan 4, 2026Updated 4 months ago
- HLS code for Network on Chip (NoC)☆22Sep 11, 2020Updated 5 years ago
- A Direct Memory Access Controller (DMAC) with AHB-lite bus interface☆17Oct 6, 2024Updated last year
- gem5 repository to study chiplet-based systems☆89Apr 18, 2019Updated 7 years ago
- HLS for Networks-on-Chip☆39Feb 18, 2021Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- The source code that empowers OpenROAD Cloud☆13Jun 29, 2020Updated 5 years ago
- Attentionlego☆13Jan 24, 2024Updated 2 years ago
- https://nvmexplorer.seas.harvard.edu NVMExplorer is a cross-stack design space exploration framework for evaluating and comparing on-chip…☆21Jun 21, 2024Updated last year
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆77Dec 30, 2019Updated 6 years ago
- Automatically exported from code.google.com/p/tpzsimul☆14Jul 7, 2015Updated 10 years ago
- ☆16Sep 15, 2023Updated 2 years ago
- AHB/APB SRAM Inf, VCS&Verdi Sim.☆16Jun 20, 2022Updated 3 years ago
- An ARMv8 virtual platform based on QEMU and VCML☆49Apr 15, 2026Updated 3 weeks ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆148Mar 19, 2018Updated 8 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆37Dec 22, 2023Updated 2 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆64Dec 15, 2025Updated 4 months ago
- Rewrite XuanTieC910 with chisel3☆12Jul 1, 2022Updated 3 years ago
- Network on Chip for MPSoC☆28Apr 19, 2026Updated 2 weeks ago
- Wrapper for ETH Ariane Core☆22Sep 2, 2025Updated 8 months ago
- Repository for "GIST: Distributed training for large-scale graph convolutional networks"☆15Jan 14, 2023Updated 3 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Aug 22, 2021Updated 4 years ago
- SystemC to Verilog Synthesizable Subset Translator☆13May 12, 2023Updated 2 years ago
- ☆12Jun 11, 2021Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- This is the source code of the 2021 replication for ReScience of the paper "Speedup Graph Processing by Graph Ordering" by Hao Wei, Jeffr…☆12May 31, 2021Updated 4 years ago
- Fork of the gem5 simulator with Garnet2.0 and DSENT extensions☆12Jan 28, 2019Updated 7 years ago
- Theia: ray graphic processing unit☆20Jul 17, 2014Updated 11 years ago
- OpenGraph is an open-source graph processing benchmarking suite written in pure C/OpenMP. Integrated with Sniper simulator.☆11Apr 27, 2024Updated 2 years ago
- ☆13Aug 8, 2024Updated last year
- ☆29Oct 20, 2019Updated 6 years ago
- muSYCL, the SYCL musical!☆13Aug 25, 2024Updated last year