Alternatives and similar repositories for libsystemctlm-soc

Users that are interested in libsystemctlm-soc are comparing it to the libraries listed below

• mariusmm / RISC-V-TLM
  RISC-V SystemC-TLM simulator
  ☆332Updated 3 weeks ago
• Xilinx / systemctlm-cosim-demo
  QEMU libsystemctlm-soc co-simulation demos.
  ☆156Updated 6 months ago
• machineware-gmbh / vcml
  A modeling library with virtual components for SystemC and TLM simulators
  ☆174Updated this week
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆221Updated 5 years ago
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆75Updated last month
• riscv-ovpsim / imperas-riscv-tests
  ☆190Updated last year
• subbdue / systemverilog.io
  Code used in
  ☆198Updated 8 years ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆194Updated 3 years ago
• tukl-msd / DRAMSys
  DRAMSys a SystemC TLM-2.0 based DRAM simulator.
  ☆320Updated 2 months ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆247Updated this week
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆302Updated 2 years ago
• Minres / SystemC-Components
  A SystemC productivity library: https://minres.github.io/SystemC-Components/
  ☆124Updated last week
• pulp-platform / pulp-riscv-gnu-toolchain
  ☆97Updated 3 months ago
• agra-uni-bremen / riscv-vp
  RISC-V Virtual Prototype
  ☆180Updated 11 months ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆186Updated last week
• learnwithexamples / learnsystemc
  Learn systemC with examples
  ☆125Updated 2 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆183Updated 3 months ago
• alexforencich / cocotbext-pcie
  PCI express simulation framework for Cocotb
  ☆181Updated 2 months ago
• NVlabs / matchlib
  SystemC/C++ library of commonly-used hardware functions and components for HLS.
  ☆287Updated last month
• intel / systemc-compiler
  This tool translates synthesizable SystemC code to synthesizable SystemVerilog.
  ☆297Updated 3 weeks ago
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆266Updated last week
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆223Updated 3 weeks ago
• cnrv / rocket-chip-read
  Comment on the rocket-chip source code
  ☆179Updated 7 years ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆126Updated 2 weeks ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆182Updated last year
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆130Updated 5 years ago
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆144Updated last year
• Juniper / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆203Updated last year
• WilsonChen003 / HDLGen
  HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…
  ☆108Updated 2 years ago
• sparcians / map
  Modeling Architectural Platform
  ☆212Updated 3 weeks ago