Alternatives and similar repositories for libsystemctlm-soc

Users that are interested in libsystemctlm-soc are comparing it to the libraries listed below

• mariusmm / RISC-V-TLM
  RISC-V SystemC-TLM simulator
  ☆304Updated 4 months ago
• Xilinx / systemctlm-cosim-demo
  QEMU libsystemctlm-soc co-simulation demos.
  ☆145Updated 11 months ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆279Updated last year
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆174Updated 2 years ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆212Updated 4 years ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆196Updated this week
• machineware-gmbh / vcml
  A modeling library with virtual components for SystemC and TLM simulators
  ☆154Updated last week
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆275Updated 2 weeks ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆201Updated this week
• alexforencich / cocotbext-pcie
  PCI express simulation framework for Cocotb
  ☆160Updated last week
• riscv-ovpsim / imperas-riscv-tests
  ☆173Updated last year
• tukl-msd / DRAMSys
  DRAMSys a SystemC TLM-2.0 based DRAM simulator.
  ☆267Updated last month
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆178Updated 5 months ago
• Juniper / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆199Updated 6 months ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆166Updated 5 months ago
• Minres / SystemC-Components
  A SystemC productivity library: https://minres.github.io/SystemC-Components/
  ☆103Updated last week
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆89Updated 2 months ago
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆251Updated 2 months ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆122Updated 6 years ago
• agra-uni-bremen / riscv-vp
  RISC-V Virtual Prototype
  ☆168Updated 5 months ago
• RV-BOSC / OpenNoC
  ☆153Updated last week
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆250Updated 3 weeks ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆147Updated last week
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆149Updated last week
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆65Updated 10 months ago
• taichi-ishitani / tvip-axi
  AMBA AXI VIP
  ☆398Updated 10 months ago
• NVlabs / matchlib
  SystemC/C++ library of commonly-used hardware functions and components for HLS.
  ☆268Updated 2 weeks ago
• chipsalliance / aib-phy-hardware
  Advanced Interface Bus (AIB) die-to-die hardware open source
  ☆136Updated 7 months ago
• chipsalliance / VeeR-ISS
  ☆134Updated last year
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆201Updated last year