Alternatives and similar repositories for libsystemctlm-soc

Users that are interested in libsystemctlm-soc are comparing it to the libraries listed below

• machineware-gmbh / vcml
  A modeling library with virtual components for SystemC and TLM simulators
  ☆172Updated last week
• mariusmm / RISC-V-TLM
  RISC-V SystemC-TLM simulator
  ☆329Updated this week
• Xilinx / systemctlm-cosim-demo
  QEMU libsystemctlm-soc co-simulation demos.
  ☆154Updated 5 months ago
• Minres / SystemC-Components
  A SystemC productivity library: https://minres.github.io/SystemC-Components/
  ☆123Updated last week
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆193Updated 3 years ago
• subbdue / systemverilog.io
  Code used in
  ☆198Updated 8 years ago
• riscv-ovpsim / imperas-riscv-tests
  ☆189Updated last year
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆218Updated 5 years ago
• agra-uni-bremen / riscv-vp
  RISC-V Virtual Prototype
  ☆179Updated 11 months ago
• intel / systemc-compiler
  This tool translates synthesizable SystemC code to synthesizable SystemVerilog.
  ☆292Updated this week
• alexforencich / cocotbext-pcie
  PCI express simulation framework for Cocotb
  ☆182Updated 2 months ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆178Updated 2 months ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆300Updated 2 years ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆185Updated last week
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆232Updated 2 weeks ago
• Juniper / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆202Updated last year
• NVlabs / matchlib
  SystemC/C++ library of commonly-used hardware functions and components for HLS.
  ☆286Updated 2 weeks ago
• tukl-msd / DRAMSys
  DRAMSys a SystemC TLM-2.0 based DRAM simulator.
  ☆316Updated last month
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆75Updated 3 weeks ago
• WilsonChen003 / HDLGen
  HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…
  ☆106Updated 2 years ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆112Updated last week
• riscv-software-src / riscv-perf-model
  Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
  ☆190Updated this week
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆202Updated last year
• pulp-platform / pulp-riscv-gnu-toolchain
  ☆96Updated 2 months ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆179Updated 11 months ago
• sparcians / map
  Modeling Architectural Platform
  ☆212Updated this week
• RV-BOSC / OpenNoC
  ☆204Updated 4 months ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆143Updated 3 weeks ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆218Updated this week
• accellera-official / uvm-core
  ☆98Updated last year