Alternatives and similar repositories for Shenjing-RTL

Users that are interested in Shenjing-RTL are comparing it to the libraries listed below

• saunak1994 / CyNAPSEv11
  The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL
  ☆34Updated 5 years ago
• jerry-D / HedgeHog-Fused-Spiking-Neural-Network-Emulator-Compute-Engine
  HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx…
  ☆60Updated 4 months ago
• snagiri / CSE237D-PYNQ-SNN-Accelerator
  Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board
  ☆36Updated 6 years ago
• Deepak42074 / SRAM_IMC_MPW8
  The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…
  ☆12Updated 2 years ago
• SFU-HiAccel / SyncNN
  [FPL 2021] SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs.
  ☆57Updated 3 years ago
• oshears / SNN-FPGA-Implementation
  ☆19Updated 4 years ago
• zwhexplorer / Spiking-Neural-Network-Accelerator-EE552-project
  Spiking Neural Network Accelerator
  ☆15Updated 3 years ago
• CestSansImportance / SNN-FPGA
  Spiking Neural Network RTL Implementation
  ☆58Updated 4 years ago
• Minz9 / SNN-on-FPGA
  SNN on FPGA
  ☆10Updated 3 years ago
• githubofaliyev / SNN-DSE
  Hardware and software implementation of Sparsely-active SNNs
  ☆14Updated 6 months ago
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆24Updated 4 years ago
• mayshin10 / CNN-Accelerator
  Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.
  ☆21Updated 4 years ago
• ChFrenkel / tinyODIN
  tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.
  ☆60Updated 2 years ago
• evan199893 / TPU_systolic_array_HW_accelerator
  Tensor Processing Unit implementation in Verilog
  ☆9Updated 3 months ago
• Spiritator / FPGA_LeNet5_ws_8x8
  FPGA implement of 8x8 weight stationary systolic array DNN accelerator
  ☆11Updated 4 years ago
• eejlny / S2NN-HLS
  Spiking neural network for Zynq devices with Vivado HLS
  ☆34Updated 7 years ago
• jeshraghian / snn-accelerator
  ☆25Updated 3 years ago
• HanPU-Code / CNN_YOLO_AI_accelerator
  This project is to design yolo AI accelerator in verilog HDL.
  ☆17Updated 9 months ago
• CodeNameGrapefruit / SoC_CNN
  Convolutional Neural Network Implemented in Verilog for System on Chip
  ☆27Updated 6 years ago
• Marco-Winzker / Spiking_NN_RGB_FPGA
  FPGA Design of a Spiking Neural Network.
  ☆41Updated last year
• trung-pham-dinh / CNN-on-FPGA
  ☆15Updated 3 years ago
• UA-RCL / RANC
  ☆47Updated last year
• yucanliu / VLSI_SNN
  A Spiking Neuron Network Project in Verilog Implementation
  ☆23Updated 7 years ago
• AIC2021 / AIC2021_TPU_Template
  Template for project1 TPU
  ☆19Updated 4 years ago
• oshears / fpga_snn_models
  A repository FPGA-friendly SNN models
  ☆34Updated 4 years ago
• NikhilMukraj / spiking-neural-networks-hardware
  An FPGA design for simulating biological neurons
  ☆15Updated last year
• nikitabuzov / SpikingNeuralNet
  Spiking neural network implementation using Verilog with LIF (Leaky Integrate-and-Fire) neurons
  ☆18Updated 5 years ago
• cepdnaclk / e17-4yp-Neuromorphic-NoC-Architecture-for-SNNs
  This project aims to develop a novel neuromorphic NoC architecture based on RISC-V ISA to support spiking neural network applications, an…
  ☆21Updated last year
• coreylammie / TCAS-STDP
  IEEE Transactions on Circuits and Systems I: Efficient FPGA Implementations of Pair and Triplet-based STDP for Neuromorphic Architectures
  ☆26Updated 6 years ago
• eda-lab / CNNAF-CNN-Accelerator
  CNN-Accelerator based on FPGA developed by verilog HDL.
  ☆10Updated 3 years ago