Angela-WangBo / Shenjing-RTLLinks
This is the RTL implementation of Shenjing, a low power neuromorphic computing accelerator
☆17Updated 5 years ago
Alternatives and similar repositories for Shenjing-RTL
Users that are interested in Shenjing-RTL are comparing it to the libraries listed below
Sorting:
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆34Updated 5 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆36Updated 5 years ago
- Spiking Neural Network Accelerator☆15Updated 3 years ago
- The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…☆11Updated 2 years ago
- HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx…☆58Updated 3 months ago
- ☆19Updated 4 years ago
- SNN on FPGA☆10Updated 3 years ago
- tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.☆56Updated 2 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆10Updated 3 years ago
- [FPL 2021] SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs.☆55Updated 3 years ago
- Spiking Neural Network RTL Implementation☆57Updated 3 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- A repository FPGA-friendly SNN models☆34Updated 4 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆11Updated 4 years ago
- ☆25Updated 2 years ago
- ☆15Updated 3 years ago
- CORDIC-SNN, followed with "Unsupervised learning of digital recognition using STDP" published in 2015, frontiers☆23Updated 5 years ago
- A Spiking Neuron Network Project in Verilog Implementation☆23Updated 7 years ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆10Updated last year
- This project aims to develop a novel neuromorphic NoC architecture based on RISC-V ISA to support spiking neural network applications, an…☆21Updated last year
- Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators☆17Updated 2 years ago
- Spiking neural network for Zynq devices with Vivado HLS☆33Updated 7 years ago
- ☆17Updated 4 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- ☆33Updated 6 years ago
- Framework for radix encoded SNN on FPGA☆13Updated 3 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- Efficient FPGA-Based Accelerator for Convolutional Neural Networks☆14Updated 10 months ago
- Hardware and software implementation of Sparsely-active SNNs☆14Updated 4 months ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆22Updated 4 years ago