adki / cosim_bfm_library
HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
☆31Updated 3 months ago
Alternatives and similar repositories for cosim_bfm_library:
Users that are interested in cosim_bfm_library are comparing it to the libraries listed below
- ☆23Updated 3 weeks ago
- YosysHQ SVA AXI Properties☆37Updated 2 years ago
- ☆25Updated 4 years ago
- Common SystemVerilog RTL modules for RgGen☆12Updated last month
- verification of simple axi-based cache☆18Updated 5 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆25Updated 5 months ago
- ☆21Updated 5 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆18Updated 7 months ago
- StateMover is a checkpoint-based debugging framework for FPGAs.☆19Updated 2 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆28Updated 2 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- PCI Express controller model☆51Updated 2 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆18Updated 2 years ago
- DUTH RISC-V Superscalar Microprocessor☆30Updated 5 months ago
- ☆19Updated 5 years ago
- Andes Vector Extension support added to riscv-dv☆14Updated 4 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆17Updated 10 months ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 4 years ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆21Updated 6 years ago
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆15Updated 10 months ago
- Xilinx AXI VIP example of use☆34Updated 3 years ago
- CORE-V MCU UVM Environment and Test Bench☆20Updated 8 months ago
- ☆14Updated last month
- Platform Level Interrupt Controller☆37Updated 10 months ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆53Updated 4 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆52Updated last week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated last month
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆28Updated last month
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated last year
- ☆13Updated 4 years ago