KevinWang96 / Chip-Multi-processor-System-based-on-Cardinal-Bidirectional-Ring-Network-on-chip
EE577b-Course-Project
☆16Updated 4 years ago
Alternatives and similar repositories for Chip-Multi-processor-System-based-on-Cardinal-Bidirectional-Ring-Network-on-chip:
Users that are interested in Chip-Multi-processor-System-based-on-Cardinal-Bidirectional-Ring-Network-on-chip are comparing it to the libraries listed below
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆30Updated 2 years ago
- ☆12Updated 9 years ago
- verification of simple axi-based cache☆18Updated 5 years ago
- RTL code of some arbitration algorithm☆13Updated 5 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆36Updated 2 years ago
- Synchronous FIFO design & verification using systemVerilog Assertions☆15Updated 3 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 6 years ago
- ☆16Updated 2 years ago
- DDR3 function verification environment in UVM☆23Updated 6 years ago
- CNN accelerator using NoC architecture☆15Updated 6 years ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆19Updated 12 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- ☆29Updated 5 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆28Updated 2 years ago
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆16Updated 2 weeks ago
- AHB-APB UVM Verification Environment☆17Updated 9 years ago
- AXI Interconnect☆47Updated 3 years ago
- ☆25Updated 4 years ago
- Design and UVM-TB of RISC -V Microprocessor☆14Updated 7 months ago
- ☆24Updated 3 years ago
- The memory model was leveraged from micron.☆22Updated 6 years ago
- UVM resource from github, run simulation use YASAsim flow☆27Updated 4 years ago
- CORE-V MCU UVM Environment and Test Bench☆18Updated 7 months ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆31Updated 2 years ago
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆22Updated 11 months ago
- Sample UVM code for axi ram dut☆30Updated 3 years ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆24Updated 2 years ago
- General Purpose AXI Direct Memory Access☆48Updated 9 months ago
- The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …☆17Updated 3 years ago
- Simple AMBA VIP, Include axi/ahb/apb☆18Updated 7 months ago