KevinWang96 / Chip-Multi-processor-System-based-on-Cardinal-Bidirectional-Ring-Network-on-chipView on GitHub
EE577b-Course-Project
☆19May 6, 2020Updated 5 years ago
Alternatives and similar repositories for Chip-Multi-processor-System-based-on-Cardinal-Bidirectional-Ring-Network-on-chip
Users that are interested in Chip-Multi-processor-System-based-on-Cardinal-Bidirectional-Ring-Network-on-chip are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- Spiking Neural Network Accelerator☆15May 18, 2022Updated 3 years ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Feb 12, 2019Updated 7 years ago
- The memory model was leveraged from micron.☆30Mar 24, 2018Updated 8 years ago
- SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).☆14Apr 20, 2014Updated 12 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆33Nov 6, 2018Updated 7 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Aug 22, 2021Updated 4 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆17Jun 24, 2020Updated 5 years ago
- Xilinx AXI VIP example of use☆43Apr 24, 2021Updated 5 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆77Dec 30, 2019Updated 6 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆14Dec 23, 2022Updated 3 years ago
- A hardware accelerator for General Matrix Multiply, developed in SystemC using ESP.☆20May 26, 2021Updated 4 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆29Dec 26, 2022Updated 3 years ago
- 多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency☆26Aug 28, 2016Updated 9 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Generic AHB master stub☆12Jul 17, 2014Updated 11 years ago
- ☆29May 11, 2021Updated 4 years ago
- DDR4 Simulation Project in System Verilog☆46Aug 18, 2014Updated 11 years ago
- Assertion-Based Formal Verification of an AHB2APB bridge, featuring SystemVerilog assertions, RTL designs, and detailed documentation inc…☆33Mar 23, 2024Updated 2 years ago
- 标准视频时序生成器☆10Feb 9, 2020Updated 6 years ago
- Verilog-Based-NoC-Simulator☆10May 4, 2016Updated 10 years ago
- Synchronous FIFO design & verification using systemVerilog Assertions☆18Aug 3, 2021Updated 4 years ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆62Dec 3, 2021Updated 4 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- FIR,FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Jan 22, 2025Updated last year
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆94Feb 28, 2018Updated 8 years ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆25Jul 6, 2018Updated 7 years ago
- HLS code for Network on Chip (NoC)☆22Sep 11, 2020Updated 5 years ago
- 位宽和深度可定制的异步FIFO☆14May 29, 2024Updated last year
- Direct Access Memory for MPSoC☆13Apr 19, 2026Updated 2 weeks ago
- UVM testbench for verifying the Pulpino SoC☆14Mar 23, 2020Updated 6 years ago
- Modular Verilog PCIexpress Interface Components with complete MyHDL Testbench for FPGA deployment☆14Sep 17, 2019Updated 6 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Plugin manager using Qt framework to create Qt application based on custom loadable plugins☆13Oct 12, 2023Updated 2 years ago
- ☆14Feb 24, 2025Updated last year
- 第四届全国大学生嵌入式比赛SoC☆11Apr 1, 2022Updated 4 years ago
- Maven Silicon Project☆19Oct 13, 2018Updated 7 years ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 11 years ago
- DMA core compatible with AHB3-Lite☆13Mar 30, 2019Updated 7 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Dec 9, 2020Updated 5 years ago