cdsc-github / parade-ara-simulatorLinks
PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration
☆48Updated 3 years ago
Alternatives and similar repositories for parade-ara-simulator
Users that are interested in parade-ara-simulator are comparing it to the libraries listed below
Sorting:
- Heterogeneous simulator for DECADES Project☆32Updated last year
- ☆91Updated last year
- The gem5-X open source framework (based on the gem5 simulator)☆41Updated 2 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆50Updated 7 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆72Updated 6 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆123Updated 5 years ago
- ☆24Updated 4 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- CGRA Compilation Framework☆84Updated last year
- ☆25Updated last year
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆42Updated 7 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- agile hardware-software co-design☆48Updated 3 years ago
- ordspecsim: The Swarm architecture simulator☆24Updated 2 years ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆31Updated 3 years ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆68Updated 11 months ago
- ☆26Updated 3 years ago
- CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube☆22Updated 6 years ago
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆31Updated last year
- DASS HLS Compiler☆29Updated last year
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆68Updated last year
- EQueue Dialect☆40Updated 3 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- ☆31Updated 2 months ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆39Updated 6 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆92Updated 8 months ago
- ☆35Updated 4 years ago
- The source code for GPGPUSim+Ramulator simulator. In this version, GPGPUSim uses Ramulator to simulate the DRAM. This simulator is used t…☆56Updated 5 years ago
- A binary instrumentation tool to analyze load instructions in any off-the-shelf x86(-64) program. Described by Bera et al. in https://arx…☆21Updated 11 months ago
- A DSL for Systolic Arrays☆79Updated 6 years ago