cdsc-github / parade-ara-simulatorLinks
PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration
☆48Updated 3 years ago
Alternatives and similar repositories for parade-ara-simulator
Users that are interested in parade-ara-simulator are comparing it to the libraries listed below
Sorting:
- ☆92Updated last year
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆75Updated 6 years ago
- Heterogeneous simulator for DECADES Project☆32Updated last year
- The gem5-X open source framework (based on the gem5 simulator)☆41Updated 2 years ago
- Release of stream-specialization software/hardware stack.☆122Updated 2 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆125Updated 5 years ago
- ☆25Updated last year
- CGRA Compilation Framework☆85Updated last year
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆42Updated 7 years ago
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆37Updated 2 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆50Updated 8 years ago
- ☆28Updated 3 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆93Updated 9 months ago
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆32Updated last year
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- EQueue Dialect☆40Updated 3 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆68Updated last year
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- Fast and accurate DRAM power and energy estimation tool☆168Updated last week
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆55Updated 4 years ago
- ordspecsim: The Swarm architecture simulator☆24Updated 2 years ago
- gem5 repository to study chiplet-based systems☆76Updated 6 years ago
- A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical pa…☆71Updated 10 months ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆31Updated 3 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆82Updated last year
- ☆24Updated 4 years ago
- The source code for GPGPUSim+Ramulator simulator. In this version, GPGPUSim uses Ramulator to simulate the DRAM. This simulator is used t…☆56Updated 5 years ago