Alternatives and similar repositories for parade-ara-simulator

Users that are interested in parade-ara-simulator are comparing it to the libraries listed below

• PrincetonUniversity / MosaicSim
  Heterogeneous simulator for DECADES Project
  ☆32Updated last year
• gthparch / HBM
  High Bandwidth Memory (HBM) timing model based on DRAMSim2
  ☆45Updated 8 years ago
• MPSLab-ASU / DiRAC
  Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators
  ☆30Updated 2 years ago
• TeCSAR-UNCC / gem5-SALAM
  ☆108Updated last year
• SwarmArch / sim
  ordspecsim: The Swarm architecture simulator
  ☆24Updated 2 years ago
• estwings57 / CasHMC
  CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube
  ☆23Updated 7 years ago
• SFU-HiAccel / uBench
  [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers
  ☆31Updated 4 years ago
• cwfletcher / buffets
  Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
  ☆81Updated 6 years ago
• CMU-SAFARI / GPGPUSim-Ramulator
  The source code for GPGPUSim+Ramulator simulator. In this version, GPGPUSim uses Ramulator to simulate the DRAM. This simulator is used t…
  ☆58Updated 6 years ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆65Updated 4 years ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆47Updated 3 years ago
• Liu-Cheng / cycle-accurate-SystemC-simulator-over-ramulator
  An example of using Ramulator as memory model in a cycle-accurate SystemC Design
  ☆55Updated 8 years ago
• breagen / MachSuite
  Benchmarks for Accelerator Design and Customized Architectures
  ☆135Updated 5 years ago
• esl-epfl / gem5-X
  The gem5-X open source framework (based on the gem5 simulator)
  ☆42Updated 2 years ago
• MPSLab-ASU / ccf
  CGRA Compilation Framework
  ☆89Updated 2 years ago
• CMU-SAFARI / VAMPIRE
  An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …
  ☆40Updated 6 years ago
• zslwyuan / PAAS_V1.0
  PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems
  ☆43Updated 4 years ago
• he-actlab / planaria.code
  ☆29Updated 4 years ago
• GT-CHIPS / gem5_chips
  gem5 repository to study chiplet-based systems
  ☆84Updated 6 years ago
• PolyArch / gem-forge-framework
  ☆26Updated 2 years ago
• baichen318 / arch-explorer
  ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis
  ☆33Updated last year
• CMU-SAFARI / Load-Inspector
  A binary instrumentation tool to analyze load instructions in any off-the-shelf x86(-64) program. Described by Bera et al. in https://arx…
  ☆23Updated last year
• Systems-ShiftLab / MultiPIM
  MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator
  ☆55Updated 4 years ago
• PolyArch / dsa-framework
  Release of stream-specialization software/hardware stack.
  ☆120Updated 2 years ago
• pku-liang / HASCO
  agile hardware-software co-design
  ☆52Updated 4 years ago
• CMU-SAFARI / Hermes
  A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical pa…
  ☆76Updated 3 months ago
• suchandler96 / gem5-NVDLA
  ☆40Updated 8 months ago
• CMU-SAFARI / PiDRAM
  PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …
  ☆70Updated 2 years ago
• stonne-simulator / sst-elements-with-stonne
  STONNE Simulator integrated into SST Simulator
  ☆22Updated last year
• tsinghua-ideal / spada-sim
  The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow
  ☆44Updated 2 years ago