PSAL-POSTECH / ONNXim
ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference
☆67Updated last week
Related projects ⓘ
Alternatives and complementary repositories for ONNXim
- NeuPIMs Simulator☆54Updated 5 months ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆38Updated 6 months ago
- ☆40Updated 4 months ago
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆56Updated 2 months ago
- An analytical framework that models hardware dataflow of tensor applications on spatial architectures using the relation-centric notation…☆80Updated 6 months ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆74Updated last year
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆40Updated last week
- ☆25Updated 3 years ago
- MICRO22 artifact evaluation for Sparseloop☆39Updated 2 years ago
- ☆87Updated 4 months ago
- A co-design architecture on sparse attention☆44Updated 3 years ago
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆52Updated this week
- ☆41Updated 3 years ago
- ☆31Updated 3 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆46Updated 2 weeks ago
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆51Updated 3 years ago
- ☆22Updated last year
- RTL implementation of Flex-DPE.☆91Updated 4 years ago
- A reference implementation of the Mind Mappings Framework.☆28Updated 2 years ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆31Updated 7 months ago
- ☆60Updated 3 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆65Updated 3 years ago
- ☆26Updated 3 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆44Updated 2 years ago
- ☆17Updated last year
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆32Updated last year
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆22Updated 5 months ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆63Updated 5 years ago
- ☆10Updated last year
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆30Updated last month