maestro-project / frameLinks
FRAME: Fast Roofline Analytical Modeling and Estimation
☆39Updated 2 years ago
Alternatives and similar repositories for frame
Users that are interested in frame are comparing it to the libraries listed below
Sorting:
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆59Updated last month
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆69Updated last month
- ☆38Updated 7 months ago
- agile hardware-software co-design☆52Updated 3 years ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆65Updated 3 weeks ago
- A Toy-Purpose TPU Simulator☆19Updated last year
- A reference implementation of the Mind Mappings Framework.☆30Updated 3 years ago
- An analytical framework that models hardware dataflow of tensor applications on spatial architectures using the relation-centric notation…☆87Updated last year
- ☆32Updated 4 years ago
- MICRO22 artifact evaluation for Sparseloop☆44Updated 3 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆82Updated 4 years ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆72Updated last year
- ☆32Updated last year
- ☆61Updated 7 months ago
- HyFiSS: A Hybrid Fidelity Stall-Aware Simulator for GPGPUs☆37Updated 11 months ago
- Domain-Specific Architecture Generator 2☆21Updated 3 years ago
- H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference☆76Updated 6 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 4 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆64Updated 4 months ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆83Updated 2 years ago
- ☆28Updated 2 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- ☆25Updated last year
- ☆35Updated 5 years ago
- ☆42Updated last year
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆91Updated last year
- ☆33Updated 4 years ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆60Updated 3 years ago
- ☆13Updated last year