OSU-STARLAB / GPGPU-Ramulator-SimulatorLinks
Replace original DRAM model in GPGPU-sim with Ramulator DRAM model
☆18Updated 6 years ago
Alternatives and similar repositories for GPGPU-Ramulator-Simulator
Users that are interested in GPGPU-Ramulator-Simulator are comparing it to the libraries listed below
Sorting:
- CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube☆22Updated 6 years ago
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆48Updated 3 years ago
- ☆33Updated 4 months ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆42Updated 8 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆46Updated 3 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆36Updated 7 months ago
- The source code for GPGPUSim+Ramulator simulator. In this version, GPGPUSim uses Ramulator to simulate the DRAM. This simulator is used t…☆57Updated 5 years ago
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- ☆36Updated 4 years ago
- cycle accurate Network-on-Chip Simulator☆28Updated 2 years ago
- A simple cycle-accurate DaDianNao simulator☆13Updated 6 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆39Updated 6 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆29Updated 2 years ago
- Processing-in Memory Architecture for Multiply-Accumulate Operations with Hybrid Memory Cube☆12Updated 8 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆64Updated 3 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated 11 months ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆26Updated 2 years ago
- ordspecsim: The Swarm architecture simulator☆25Updated 2 years ago
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆14Updated 10 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆28Updated 2 weeks ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆51Updated 8 years ago
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆13Updated 4 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆68Updated last year
- HLS project modeling various sparse accelerators.☆13Updated 3 years ago
- ☆25Updated last year
- DASS HLS Compiler☆29Updated last year
- ☆27Updated 5 years ago
- A Vector Caching Scheme for Streaming FPGA SpMV Accelerators☆10Updated 9 years ago
- A parallel and distributed simulator for thousand-core chips☆24Updated 7 years ago