GATECH-EIC / ViTALiTyLinks
ViTALiTy (HPCA'23) Code Repository
☆22Updated 2 years ago
Alternatives and similar repositories for ViTALiTy
Users that are interested in ViTALiTy are comparing it to the libraries listed below
Sorting:
- An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences☆27Updated last year
- ☆45Updated 3 years ago
- ☆41Updated 5 months ago
- A co-design architecture on sparse attention☆52Updated 3 years ago
- [HPCA 2023] ViTCoD: Vision Transformer Acceleration via Dedicated Algorithm and Accelerator Co-Design☆107Updated last year
- ☆27Updated this week
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆43Updated last year
- [HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning☆93Updated 9 months ago
- Tender: Accelerating Large Language Models via Tensor Decompostion and Runtime Requantization (ISCA'24)☆14Updated 11 months ago
- ☆18Updated 2 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆16Updated 10 months ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆32Updated this week
- ☆27Updated 2 months ago
- [FPGA 2024]FPGA Accelerator for Imbalanced SpMV using HLS☆12Updated 3 months ago
- Open-source of MSD framework☆16Updated last year
- A DAG processor and compiler for a tree-based spatial datapath.☆13Updated 2 years ago
- ☆34Updated 4 years ago
- MICRO22 artifact evaluation for Sparseloop☆43Updated 2 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆39Updated 2 years ago
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆36Updated last year
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆77Updated 3 years ago
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆25Updated 2 years ago
- Serpens is an HBM FPGA accelerator for SpMV☆19Updated 10 months ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆56Updated 4 months ago
- Implementation of Microscaling data formats in SystemVerilog.☆19Updated 9 months ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆53Updated 2 months ago
- ☆12Updated last year
- ☆44Updated 2 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆52Updated last month