GATECH-EIC / ViTALiTyLinks
ViTALiTy (HPCA'23) Code Repository
☆23Updated 2 years ago
Alternatives and similar repositories for ViTALiTy
Users that are interested in ViTALiTy are comparing it to the libraries listed below
Sorting:
- An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences☆30Updated last year
- [HPCA 2023] ViTCoD: Vision Transformer Acceleration via Dedicated Algorithm and Accelerator Co-Design☆124Updated 2 years ago
- ☆47Updated 4 years ago
- [HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning☆115Updated last year
- A co-design architecture on sparse attention☆54Updated 4 years ago
- ☆32Updated last week
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆54Updated 2 years ago
- Open-source of MSD framework☆16Updated 2 years ago
- ☆28Updated last month
- H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference☆77Updated 7 months ago
- [TRETS 2025][FPGA 2024] FPGA Accelerator for Imbalanced SpMV using HLS☆17Updated 3 months ago
- ☆25Updated 9 months ago
- Implementation of Microscaling data formats in SystemVerilog.☆28Updated 5 months ago
- ASIC simulation of Multi-ported Memory Module. And it can offer SRAM-based dual-port basic building block to support multiple read/write …☆21Updated 9 years ago
- ☆31Updated 8 months ago
- A bit-level sparsity-awared multiply-accumulate process element.☆18Updated last year
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆35Updated this week
- ☆112Updated 2 years ago
- MICRO 2024 Evaluation Artifact for FuseMax☆16Updated last year
- ☆35Updated 5 years ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆42Updated 2 years ago
- ☆18Updated 2 years ago
- MICRO22 artifact evaluation for Sparseloop☆44Updated 3 years ago
- Tender: Accelerating Large Language Models via Tensor Decompostion and Runtime Requantization (ISCA'24)☆24Updated last year
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆71Updated last month
- PyTorchSim is a Comprehensive, Fast, and Accurate NPU Simulation Framework☆58Updated this week
- bitfusion verilog implementation☆12Updated 3 years ago
- ☆50Updated last week
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆45Updated last year
- (Verilog) A simple convolution layer implementation with systolic array structure☆13Updated 3 years ago