estwings57 / CasHMC
CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube
☆20Updated 6 years ago
Alternatives and similar repositories for CasHMC:
Users that are interested in CasHMC are comparing it to the libraries listed below
- Hybrid Memory Cube Simulation & Research Infrastructure☆15Updated last year
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆41Updated 7 years ago
- GNNear: Accelerating Full-Batch Training of Graph NeuralNetworks with Near-Memory Processing☆13Updated 2 years ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆45Updated 2 months ago
- ☆25Updated 3 years ago
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆53Updated 3 years ago
- Processing-in Memory Architecture for Multiply-Accumulate Operations with Hybrid Memory Cube☆11Updated 8 years ago
- A Cycle-level simulator for M2NDP☆23Updated 2 months ago
- STONNE Simulator integrated into SST Simulator☆17Updated 10 months ago
- ☆23Updated 4 years ago
- ☆63Updated 4 years ago
- A fast, accurate, and easy-to-integrate memory simulator that model memory system performance with bandwidth--latency curves.☆20Updated 2 months ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆30Updated 3 years ago
- The Artifact of NeoMem: Hardware/Software Co-Design for CXL-Native Memory Tiering☆42Updated 6 months ago
- ☆13Updated last year
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆32Updated 2 years ago
- ☆24Updated last year
- The source code for GPGPUSim+Ramulator simulator. In this version, GPGPUSim uses Ramulator to simulate the DRAM. This simulator is used t…☆50Updated 5 years ago
- PIM-DL: Expanding the Applicability of Commodity DRAM-PIMs for Deep Learning via Algorithm-System Co-Optimization☆28Updated last year
- ordspecsim: The Swarm architecture simulator☆24Updated 2 years ago
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- ☆16Updated 2 years ago
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆31Updated last year
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 2 years ago
- Gem5 with PCI Express integrated.☆16Updated 6 years ago
- ☆27Updated 8 months ago
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆46Updated 2 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆17Updated 6 years ago