Alternatives and similar repositories for CasHMC

Users that are interested in CasHMC are comparing it to the libraries listed below

• tactcomplabs / gc64-hmcsim
  Hybrid Memory Cube Simulation & Research Infrastructure
  ☆17Updated 2 weeks ago
• PKUZHOU / GNNear-PACT-2022
  GNNear: Accelerating Full-Batch Training of Graph NeuralNetworks with Near-Memory Processing
  ☆13Updated 2 years ago
• Systems-ShiftLab / MultiPIM
  MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator
  ☆55Updated 4 years ago
• he-actlab / planaria.code
  ☆26Updated 3 years ago
• NeuraChip / neurachip
  NeuraChip Accelerator Simulator
  ☆12Updated last year
• stonne-simulator / sst-elements-with-stonne
  STONNE Simulator integrated into SST Simulator
  ☆19Updated last year
• gthparch / HBM
  High Bandwidth Memory (HBM) timing model based on DRAMSim2
  ☆42Updated 7 years ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆45Updated 3 years ago
• estwings57 / HMC-MAC
  Processing-in Memory Architecture for Multiply-Accumulate Operations with Hybrid Memory Cube
  ☆12Updated 8 years ago
• SFU-HiAccel / uBench
  [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers
  ☆31Updated 3 years ago
• tsinghua-ideal / spada-sim
  The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow
  ☆37Updated 2 years ago
• scalesim-project / krittika
  Heterogenous ML accelerator
  ☆18Updated last month
• kartik-hegde / mindmappings
  A reference implementation of the Mind Mappings Framework.
  ☆29Updated 3 years ago
• Yinxiao-Feng / chiplet-network-sim
  ☆33Updated 2 weeks ago
• Accelergy-Project / processing-in-memory-design
  ☆25Updated last year
• PSAL-POSTECH / M2NDP-public
  A Cycle-level simulator for M2NDP
  ☆28Updated last month
• ucb-bar / cosa
  A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)
  ☆81Updated last year
• maestro-project / magma
  ☆16Updated 3 years ago
• PolyArch / gem-forge-framework
  ☆25Updated last year
• UCLA-VAST / hbmbench
  ☆24Updated 4 years ago
• FCAS-LAB / Chiplet-Gem5-SharedMemory
  ☆31Updated last year
• suchandler96 / gem5-NVDLA
  ☆31Updated 2 months ago
• CMU-SAFARI / GPGPUSim-Ramulator
  The source code for GPGPUSim+Ramulator simulator. In this version, GPGPUSim uses Ramulator to simulate the DRAM. This simulator is used t…
  ☆56Updated 5 years ago
• cdsc-github / parade-ara-simulator
  PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration
  ☆48Updated 3 years ago
• CMU-SAFARI / SimplePIM
  SimplePIM is the first high-level programming framework for real-world processing-in-memory (PIM) architectures. Described in the PACT 20…
  ☆27Updated last year
• sparsh0mittal / destiny_3d_cache
  Source code for DESTINY, a tool for modeling 2D and 3D caches designed with SRAM, eDRAM, STT-RAM, ReRAM and PCM. This is mirror of follow…
  ☆23Updated 6 months ago
• miglopst / PIM_NDP_papers
  ☆65Updated 4 years ago
• GD06 / mpu-sim_distribution
  ☆17Updated 2 years ago
• synergy-noc-generators / Proteus
  ☆10Updated 2 years ago
• OSU-STARLAB / GPGPU-Ramulator-Simulator
  Replace original DRAM model in GPGPU-sim with Ramulator DRAM model
  ☆18Updated 6 years ago