estwings57 / CasHMC
CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube
☆20Updated 6 years ago
Related projects: ⓘ
- Hybrid Memory Cube Simulation & Research Infrastructure☆14Updated 8 months ago
- STONNE Simulator integrated into SST Simulator☆15Updated 5 months ago
- Processing-in Memory Architecture for Multiply-Accumulate Operations with Hybrid Memory Cube☆11Updated 7 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆41Updated 7 years ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆31Updated 4 months ago
- ☆25Updated 2 years ago
- GNNear: Accelerating Full-Batch Training of Graph NeuralNetworks with Near-Memory Processing☆11Updated 2 years ago
- Domain-Specific Architecture Generator 2☆20Updated last year
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆28Updated 2 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆44Updated 2 years ago
- Heterogenous ML accelerator☆15Updated 5 months ago
- ordspecsim: The Swarm architecture simulator☆23Updated last year
- A reference implementation of the Mind Mappings Framework.☆26Updated 2 years ago
- The source code for GPGPUSim+Ramulator simulator. In this version, GPGPUSim uses Ramulator to simulate the DRAM. This simulator is used t…☆45Updated 4 years ago
- ☆21Updated 11 months ago
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆30Updated 6 months ago
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆51Updated 3 years ago
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆26Updated last year
- ☆23Updated 3 years ago
- ☆16Updated 2 years ago
- agile hardware-software co-design☆42Updated 2 years ago
- ☆30Updated 3 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆41Updated 3 years ago
- ☆60Updated 3 years ago
- Source code for DESTINY, a tool for modeling 2D and 3D caches designed with SRAM, eDRAM, STT-RAM, ReRAM and PCM. This is mirror of follow…☆20Updated 8 years ago
- ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference☆43Updated last week
- NeuroSpector: Dataflow and Mapping Optimization of Deep Neural Network Accelerators☆16Updated 4 months ago
- ☆23Updated 4 months ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆26Updated last year
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆60Updated 2 years ago