estwings57 / CasHMC
CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube
☆20Updated 6 years ago
Alternatives and similar repositories for CasHMC:
Users that are interested in CasHMC are comparing it to the libraries listed below
- Hybrid Memory Cube Simulation & Research Infrastructure☆16Updated last year
- GNNear: Accelerating Full-Batch Training of Graph NeuralNetworks with Near-Memory Processing☆13Updated 2 years ago
- STONNE Simulator integrated into SST Simulator☆17Updated 11 months ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆41Updated 7 years ago
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆53Updated 3 years ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆48Updated 3 months ago
- ☆25Updated 3 years ago
- NeuraChip Accelerator Simulator☆11Updated 10 months ago
- ☆24Updated last year
- Heterogenous ML accelerator☆18Updated 5 months ago
- A Cycle-level simulator for M2NDP☆25Updated 3 months ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆30Updated 3 years ago
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆34Updated 2 years ago
- The Artifact of NeoMem: Hardware/Software Co-Design for CXL-Native Memory Tiering☆44Updated 7 months ago
- Artifact for paper "PIM is All You Need: A CXL-Enabled GPU-Free System for LLM Inference", ASPLOS 2025☆37Updated this week
- A reference implementation of the Mind Mappings Framework.☆29Updated 3 years ago
- Processing-in Memory Architecture for Multiply-Accumulate Operations with Hybrid Memory Cube☆11Updated 8 years ago
- ordspecsim: The Swarm architecture simulator☆24Updated 2 years ago
- PIM-DL: Expanding the Applicability of Commodity DRAM-PIMs for Deep Learning via Algorithm-System Co-Optimization☆27Updated last year
- Graph accelerator on FPGAs and ASICs☆12Updated 6 years ago
- ☆66Updated 4 years ago
- The source code for GPGPUSim+Ramulator simulator. In this version, GPGPUSim uses Ramulator to simulate the DRAM. This simulator is used t…☆51Updated 5 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆38Updated 6 years ago
- ☆26Updated 11 months ago
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- agile hardware-software co-design☆47Updated 3 years ago
- A fast, accurate, and easy-to-integrate memory simulator that model memory system performance with bandwidth--latency curves.☆24Updated 3 weeks ago
- ☆29Updated 3 months ago
- ☆14Updated last year
- ☆9Updated 2 months ago