☆18Feb 13, 2021Updated 5 years ago
Alternatives and similar repositories for Systolic-CNN
Users that are interested in Systolic-CNN are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- An OpenCL-Based FPGA Accelerator for Compressed YOLOv2☆38May 27, 2021Updated 5 years ago
- [DATE 2025] Official implementation and dataset of AIrchitect v2: Learning the Hardware Accelerator Design Space through Unified Represen…☆20Jan 17, 2025Updated last year
- ☆31Dec 12, 2022Updated 3 years ago
- Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis☆24Jul 29, 2022Updated 3 years ago
- ☆12Mar 14, 2023Updated 3 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- OpenCL HLS based CNN Accelerator on Intel DE10 Nano FPGA.☆82Oct 3, 2023Updated 2 years ago
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆23Oct 1, 2022Updated 3 years ago
- HLS project modeling various sparse accelerators.☆12Jan 11, 2022Updated 4 years ago
- ☆50Mar 31, 2026Updated 3 months ago
- ☆15Jun 4, 2024Updated 2 years ago
- ☆32Aug 21, 2021Updated 4 years ago
- [FPGA-2022] N3H-Core: Neuron-designed Neural Network Accelerator via FPGA-based Heterogeneous Computing Cores☆11Dec 16, 2021Updated 4 years ago
- ☆15Nov 12, 2023Updated 2 years ago
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆47Jan 26, 2023Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- including compiler to encode DGL GNN model to instructions, runtime software to transfer data and control the accelerator, and hardware v…☆14Nov 19, 2023Updated 2 years ago
- CPA (Correlation Power Analysis) attacks against the AES (Advanced Encryption Standard)☆24Jul 24, 2017Updated 8 years ago
- [TCAD 2021] Block Convolution: Towards Memory-Efficient Inference of Large-Scale CNNs on FPGA☆17Jul 7, 2022Updated 4 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆95Jul 26, 2024Updated last year
- Repository for compilation and cycle-accurate simulator for scale-out systolic arrays☆16Jan 4, 2023Updated 3 years ago
- ☆17Jun 25, 2024Updated 2 years ago
- An HBM FPGA based SpMV Accelerator☆19Aug 29, 2024Updated last year
- BLAS implementation for Intel FPGA☆78Nov 18, 2020Updated 5 years ago
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆12Jun 25, 2020Updated 6 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆37Jan 20, 2022Updated 4 years ago
- HW/SW co-design of sentence-level energy optimizations for latency-aware multi-task NLP inference☆54Mar 24, 2024Updated 2 years ago
- A graph linear algebra overlay☆52Apr 26, 2023Updated 3 years ago
- Memory Benchmark for OpenCL-supported Intel FPGAs☆12Dec 25, 2023Updated 2 years ago
- NeuraChip Accelerator Simulator☆16Apr 26, 2024Updated 2 years ago
- [FPGA 2020] Open sourced implementation for the ACM/SIGDA FPGA '20 paper titled "GraphACT: Accelerating GCN Training on CPU-FPGA Heteroge…☆19Mar 6, 2021Updated 5 years ago
- An accelerator for high-dimensional approximate nearest neighbor search☆15May 17, 2025Updated last year
- An HLS based winograd systolic CNN accelerator☆54Jul 18, 2021Updated 5 years ago
- Sparse CNN Accelerator targeting Intel FPGA☆15Aug 26, 2021Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Project aimed at implementing floating point operators using the DSP48E1 slice.☆30Mar 29, 2013Updated 13 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆22Dec 10, 2022Updated 3 years ago
- Serpens is an HBM FPGA accelerator for SpMV☆23Jul 26, 2024Updated last year
- [TRETS 2025][FPGA 2024] FPGA Accelerator for Imbalanced SpMV using HLS☆23Aug 24, 2025Updated 10 months ago
- ☆39Dec 10, 2019Updated 6 years ago
- DASS HLS Compiler☆31Oct 4, 2023Updated 2 years ago
- ☆87Mar 5, 2024Updated 2 years ago