PSCLab-ASU / Systolic-CNN
☆15Updated 4 years ago
Alternatives and similar repositories for Systolic-CNN:
Users that are interested in Systolic-CNN are comparing it to the libraries listed below
- Designs for finalist teams of the DAC System Design Contest☆36Updated 4 years ago
- ☆33Updated 6 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 2 years ago
- An HLS based winograd systolic CNN accelerator☆50Updated 3 years ago
- ☆70Updated 5 years ago
- ☆26Updated 3 months ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- Fast Emulation of Approximate DNN Accelerators in PyTorch☆22Updated last year
- ☆19Updated 2 years ago
- [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)☆41Updated 3 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆70Updated 3 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- ☆14Updated last year
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆23Updated 2 years ago
- Implementation of Input Stationary, Weight Stationary and Output Stationary dataflow for given neural network on a tiled architecture☆9Updated 4 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆50Updated 2 weeks ago
- Sparse CNN Accelerator targeting Intel FPGA☆11Updated 3 years ago
- ACM TODAES Best Paper Award, 2022☆24Updated last year
- An OpenCL-Based FPGA Accelerator for Compressed YOLOv2☆37Updated 3 years ago
- ☆16Updated last year
- ☆71Updated 2 years ago
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆10Updated 4 years ago
- Open-source of MSD framework☆16Updated last year
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆57Updated 3 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- ☆9Updated 2 years ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆37Updated 2 years ago
- ☆26Updated 11 months ago
- A reference implementation of the Mind Mappings Framework.☆29Updated 3 years ago
- Code for paper "FuSeConv Fully Separable Convolutions for Fast Inference on Systolic Arrays" published at DATE 2021☆14Updated 3 years ago