cucapra / latte21Links
Languages, Tools, and Techniques for Accelerator Design
☆33Updated 3 years ago
Alternatives and similar repositories for latte21
Users that are interested in latte21 are comparing it to the libraries listed below
Sorting:
- ☆104Updated 3 years ago
- A Hardware Pipeline Description Language☆48Updated 3 months ago
- ☆27Updated 3 years ago
- FPGA synthesis tool powered by program synthesis☆51Updated 2 weeks ago
- A Language for Closed-form High-level ARchitecture Modeling☆21Updated 5 years ago
- Chisel library for Unum Type-III Posit Arithmetic☆44Updated 6 months ago
- A polyhedral compiler for hardware accelerators☆59Updated last year
- Time-sensitive affine types for predictable hardware generation☆145Updated this week
- ☆40Updated 4 years ago
- The Shang high-level synthesis framework☆120Updated 11 years ago
- Productive and portable performance programming across spatial architectures (FPGAs, etc.) and vector architectures (GPUs, etc.)☆31Updated last year
- CoreIR Symbolic Analyzer☆74Updated 4 years ago
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆67Updated 8 years ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆51Updated 2 years ago
- ILA Model Database☆23Updated 5 years ago
- ☆11Updated 3 years ago
- Polyhedral High-Level Synthesis in MLIR☆34Updated 2 years ago
- Verilog AST☆21Updated last year
- RTLCheck☆22Updated 7 years ago
- ☆29Updated 8 years ago
- An LLVM pass to prove that an II works for the given loop for Vitis HLS☆11Updated 4 years ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Updated 5 years ago
- HeteroCL-MLIR dialect for accelerator design☆41Updated last year
- DASS HLS Compiler☆29Updated 2 years ago
- ☆56Updated 3 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆22Updated last week
- DATuner Repository☆17Updated 7 years ago
- Stencil with Optimized Dataflow Architecture☆17Updated last year
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated last month