MLSys 2021 paper: MicroRec: efficient recommendation inference by hardware and data structure solutions
☆19May 26, 2021Updated 4 years ago
Alternatives and similar repositories for FPGA-Recommendation-Accelerator
Users that are interested in FPGA-Recommendation-Accelerator are comparing it to the libraries listed below
Sorting:
- ☆24Dec 1, 2020Updated 5 years ago
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆16May 26, 2021Updated 4 years ago
- ☆28Feb 26, 2023Updated 3 years ago
- (elastic) cuckoo hashing☆16Jun 20, 2020Updated 5 years ago
- ☆13Jun 20, 2023Updated 2 years ago
- ☆32Aug 21, 2021Updated 4 years ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆31Dec 16, 2021Updated 4 years ago
- Virtualized Accelerator Orchestration for Multi-Tenant Workloads☆19Nov 17, 2024Updated last year
- ☆13Oct 8, 2024Updated last year
- A simulation framework for modeling efficiency of Graph Neural Network Dataflows☆23Feb 14, 2025Updated last year
- ☆23May 30, 2025Updated 9 months ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆21Dec 10, 2022Updated 3 years ago
- Heterogenous ML accelerator☆20May 5, 2025Updated 9 months ago
- STONNE Simulator integrated into SST Simulator☆22Apr 5, 2024Updated last year
- Tutorial Material from the SST Team☆25Aug 5, 2025Updated 6 months ago
- Artifact of ASPLOS'23 paper entitled: GRACE: A Scalable Graph-Based Approach to Accelerating Recommendation Model Inference☆19Mar 5, 2023Updated 2 years ago
- ☆44Jun 30, 2024Updated last year
- TEE hardware - based on the chipyard repository - hardware to accelerate TEE☆24Dec 16, 2022Updated 3 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆64Oct 14, 2025Updated 4 months ago
- An FPGA-based NetTLP adapter☆27Mar 10, 2020Updated 5 years ago
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆25Oct 1, 2022Updated 3 years ago
- ☆29Oct 20, 2019Updated 6 years ago
- Centaur, a framework for hybrid CPU-FPGA databases☆28May 2, 2017Updated 8 years ago
- FlashMob is a shared-memory random walk system.☆32Jul 7, 2023Updated 2 years ago
- Deploy CNN accelerator in embedded OS using SDSOC and Xilinx Ultrascale+ ZCU102 platform.☆25Jul 12, 2018Updated 7 years ago
- MAESTRO binary release☆22Nov 14, 2019Updated 6 years ago
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆36Feb 21, 2024Updated 2 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆35Sep 30, 2020Updated 5 years ago
- ☆29Nov 5, 2021Updated 4 years ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆72Dec 29, 2025Updated 2 months ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Jan 3, 2023Updated 3 years ago
- Development repository for integrating FlexFlow (A distributed deep learning framework that supports flexible parallelization strategies)…☆29Oct 12, 2021Updated 4 years ago
- DAG-based blockchain☆10Apr 20, 2019Updated 6 years ago
- DRAMSim2: A cycle accurate DRAM simulator☆294Nov 11, 2020Updated 5 years ago
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆31Apr 28, 2020Updated 5 years ago
- Languages, Tools, and Techniques for Accelerator Design☆33Nov 2, 2021Updated 4 years ago
- ☆13Jan 28, 2026Updated last month
- MATLAB/Octave generator of Hamming ECC coding. Output format is Verilog HDL.☆12Dec 27, 2022Updated 3 years ago
- to study xilinx fpga using Zybo Z7-20 board☆14Mar 13, 2024Updated last year