enjoy-digital / litepcieLinks
Small footprint and configurable PCIe core
☆575Updated last month
Alternatives and similar repositories for litepcie
Users that are interested in litepcie are comparing it to the libraries listed below
Sorting:
- Small footprint and configurable DRAM core☆433Updated last month
- Bus bridges and other odds and ends☆582Updated 4 months ago
- Documenting the Xilinx 7-series bit-stream format.☆818Updated 2 months ago
- IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…☆585Updated 3 weeks ago
- A simple, basic, formally verified UART controller☆309Updated last year
- Public repository for Litefury & Nitefury☆298Updated last year
- A simple RISC-V processor for use in FPGA designs.☆279Updated last year
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆292Updated last week
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆273Updated 5 years ago
- A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz☆413Updated last month
- Linux on LiteX-VexRiscv☆655Updated last month
- A full-speed device-side USB peripheral core written in Verilog.☆236Updated 2 years ago
- A self-contained online book containing a library of FPGA design modules and related coding/design guides.☆444Updated 11 months ago
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆674Updated last month
- A huge VHDL library for FPGA and digital ASIC development☆393Updated this week
- A DDR3 memory controller in Verilog for various FPGAs☆502Updated 3 years ago
- A huge collection of VHDL/Verilog open-source IP cores scraped from the web☆513Updated 2 years ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,325Updated this week
- Opensource DDR3 Controller☆381Updated 2 months ago
- Small footprint and configurable Ethernet core☆255Updated 3 weeks ago
- AXI, AXI stream, Ethernet, and PCIe components in System Verilog☆345Updated 2 weeks ago
- LiteX boards files☆422Updated 3 weeks ago
- SystemVerilog to Verilog conversion☆659Updated 2 months ago
- UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …☆402Updated this week
- 720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)☆282Updated 4 years ago
- Common SystemVerilog components☆649Updated this week
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆438Updated 3 months ago
- A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …☆671Updated 2 weeks ago
- CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.☆279Updated 5 years ago
- VeeR EH1 core☆889Updated 2 years ago