enjoy-digital / litepcie
Small footprint and configurable PCIe core
☆521Updated this week
Alternatives and similar repositories for litepcie:
Users that are interested in litepcie are comparing it to the libraries listed below
- Small footprint and configurable DRAM core☆396Updated 2 months ago
- Bus bridges and other odds and ends☆523Updated last month
- A huge VHDL library for FPGA development☆378Updated this week
- A simple, basic, formally verified UART controller☆290Updated last year
- Documenting the Xilinx 7-series bit-stream format.☆786Updated this week
- A self-contained online book containing a library of FPGA design modules and related coding/design guides.☆418Updated 6 months ago
- IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…☆573Updated 4 years ago
- LiteX boards files☆394Updated last week
- A DDR3 memory controller in Verilog for various FPGAs☆421Updated 3 years ago
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆646Updated 3 months ago
- Public repository for Litefury & Nitefury☆283Updated 8 months ago
- USB3 PIPE interface for Xilinx 7-Series☆209Updated 2 years ago
- A simple RISC-V processor for use in FPGA designs.☆269Updated 6 months ago
- Example designs for FPGA Drive FMC☆237Updated 2 months ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,250Updated this week
- Verilog PCI express components☆1,236Updated 10 months ago
- SystemVerilog to Verilog conversion☆600Updated 2 weeks ago
- Various HDL (Verilog) IP Cores☆748Updated 3 years ago
- Small footprint and configurable Ethernet core☆223Updated last week
- Linux on LiteX-VexRiscv☆616Updated this week
- UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …☆388Updated 3 weeks ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆265Updated 4 years ago
- Common SystemVerilog components☆583Updated 2 weeks ago
- RISC-V CPU Core☆317Updated 9 months ago
- A full-speed device-side USB peripheral core written in Verilog.☆228Updated 2 years ago
- mor1kx - an OpenRISC 1000 processor IP core☆520Updated 5 months ago
- A directory of Western Digital’s RISC-V SweRV Cores☆861Updated 4 years ago
- A Verilog implementation of DisplayPort protocol for FPGAs☆242Updated 5 years ago
- VeeR EH1 core☆858Updated last year
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆280Updated last week