enjoy-digital / litedramLinks
Small footprint and configurable DRAM core
☆450Updated 3 weeks ago
Alternatives and similar repositories for litedram
Users that are interested in litedram are comparing it to the libraries listed below
Sorting:
- Small footprint and configurable PCIe core☆629Updated last week
- A simple, basic, formally verified UART controller☆312Updated last year
- Bus bridges and other odds and ends☆602Updated 6 months ago
- A simple RISC-V processor for use in FPGA designs.☆281Updated last year
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆295Updated this week
- Linux on LiteX-VexRiscv☆667Updated 2 months ago
- Experimental flows using nextpnr for Xilinx devices☆245Updated last year
- FuseSoC-based SoC for VeeR EH1 and EL2☆331Updated 11 months ago
- Opensource DDR3 Controller☆390Updated 5 months ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆277Updated 5 years ago
- FOSS Flow For FPGA☆412Updated 10 months ago
- A self-contained online book containing a library of FPGA design modules and related coding/design guides.☆451Updated last year
- A full-speed device-side USB peripheral core written in Verilog.☆235Updated 3 years ago
- Example designs showing different ways to use F4PGA toolchains.☆276Updated last year
- RISC-V CPU Core☆392Updated 4 months ago
- RISC-V Debug Support for our PULP RISC-V Cores☆278Updated 3 weeks ago
- A 32-bit RISC-V soft processor☆316Updated 3 months ago
- Small footprint and configurable Ethernet core☆268Updated this week
- LiteX boards files☆444Updated 2 weeks ago
- 720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)☆285Updated 4 years ago
- VeeR EL2 Core☆303Updated this week
- SoC based on VexRiscv and ICE40 UP5K☆158Updated 7 months ago
- A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz☆412Updated last week
- RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)☆328Updated 3 years ago
- ☆247Updated 2 years ago
- SystemVerilog to Verilog conversion☆671Updated last week
- A DDR3 memory controller in Verilog for various FPGAs☆528Updated 4 years ago
- ☆301Updated 2 weeks ago
- A Linux-capable RISC-V multicore for and by the world☆744Updated this week
- Documenting the Xilinx 7-series bit-stream format.☆833Updated 5 months ago