enjoy-digital / litedramLinks
Small footprint and configurable DRAM core
☆460Updated 3 weeks ago
Alternatives and similar repositories for litedram
Users that are interested in litedram are comparing it to the libraries listed below
Sorting:
- Small footprint and configurable PCIe core☆647Updated last month
- A simple RISC-V processor for use in FPGA designs.☆283Updated last year
- Bus bridges and other odds and ends☆612Updated 8 months ago
- A simple, basic, formally verified UART controller☆318Updated last year
- FuseSoC-based SoC for VeeR EH1 and EL2☆335Updated last year
- Linux on LiteX-VexRiscv☆672Updated 2 weeks ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆278Updated 5 years ago
- Opensource DDR3 Controller☆402Updated 6 months ago
- RISC-V CPU Core☆400Updated 5 months ago
- VeeR EL2 Core☆310Updated last week
- A self-contained online book containing a library of FPGA design modules and related coding/design guides.☆457Updated last year
- FOSS Flow For FPGA☆415Updated 11 months ago
- A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …☆692Updated 2 weeks ago
- RISC-V Debug Support for our PULP RISC-V Cores☆287Updated this week
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆298Updated last week
- Small footprint and configurable Ethernet core☆272Updated last month
- A full-speed device-side USB peripheral core written in Verilog.☆235Updated 3 years ago
- Experimental flows using nextpnr for Xilinx devices☆250Updated last year
- Example designs showing different ways to use F4PGA toolchains.☆281Updated last year
- CORE-V Family of RISC-V Cores☆310Updated 10 months ago
- Common SystemVerilog components☆689Updated this week
- SystemVerilog to Verilog conversion☆686Updated last month
- LiteX boards files☆449Updated last week
- ☆250Updated 3 years ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆451Updated 7 months ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆549Updated 2 months ago
- A Linux-capable RISC-V multicore for and by the world☆751Updated last month
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆249Updated last year
- A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz☆412Updated last month
- ☆301Updated last month