Alternatives and similar repositories for litedram

Users that are interested in litedram are comparing it to the libraries listed below

• enjoy-digital / litepcie
  Small footprint and configurable PCIe core
  ☆585Updated last month
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆311Updated last year
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆279Updated last year
• litex-hub / linux-on-litex-vexriscv
  Linux on LiteX-VexRiscv
  ☆659Updated 3 weeks ago
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆295Updated this week
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆589Updated 5 months ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆324Updated 9 months ago
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆245Updated 11 months ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆277Updated 5 years ago
• laforest / FPGADesignElements
  A self-contained online book containing a library of FPGA design modules and related coding/design guides.
  ☆447Updated last year
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆407Updated 8 months ago
• chipsalliance / f4pga-examples
  Example designs showing different ways to use F4PGA toolchains.
  ☆277Updated last year
• RoaLogic / RV12
  RISC-V CPU Core
  ☆387Updated 3 months ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆273Updated last week
• enjoy-digital / liteeth
  Small footprint and configurable Ethernet core
  ☆259Updated last month
• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆384Updated 3 months ago
• chipsalliance / Cores-VeeR-EH2
  ☆244Updated 2 years ago
• RHSResearchLLC / NiteFury-and-LiteFury
  Public repository for Litefury & Nitefury
  ☆300Updated last year
• YosysHQ / prjtrellis
  Documenting the Lattice ECP5 bit-stream format.
  ☆427Updated 2 weeks ago
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆160Updated 6 months ago
• f32c / f32c
  A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz
  ☆413Updated last week
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆297Updated this week
• litex-hub / litex-boards
  LiteX boards files
  ☆434Updated last week
• avakar / usbcorev
  A full-speed device-side USB peripheral core written in Verilog.
  ☆236Updated 2 years ago
• SpinalHDL / NaxRiscv
  ☆297Updated last week
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆738Updated last week
• minerva-cpu / minerva
  A 32-bit RISC-V soft processor
  ☆316Updated 2 months ago
• ZipCPU / sdspi
  SD-Card controller, using either SPI, SDIO, or eMMC interfaces
  ☆315Updated 5 months ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆245Updated 10 months ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆660Updated last week