enjoy-digital / litedramLinks
Small footprint and configurable DRAM core
☆464Updated 2 weeks ago
Alternatives and similar repositories for litedram
Users that are interested in litedram are comparing it to the libraries listed below
Sorting:
- Small footprint and configurable PCIe core☆657Updated this week
- A simple RISC-V processor for use in FPGA designs.☆283Updated last year
- FuseSoC-based SoC for VeeR EH1 and EL2☆334Updated last year
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆284Updated 5 years ago
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆301Updated this week
- A simple, basic, formally verified UART controller☆321Updated 2 years ago
- Experimental flows using nextpnr for Xilinx devices☆253Updated last year
- Bus bridges and other odds and ends☆631Updated 9 months ago
- Linux on LiteX-VexRiscv☆682Updated last month
- Example designs showing different ways to use F4PGA toolchains.☆282Updated last year
- A self-contained online book containing a library of FPGA design modules and related coding/design guides.☆460Updated last year
- Opensource DDR3 Controller☆413Updated 2 weeks ago
- FOSS Flow For FPGA☆423Updated last year
- A full-speed device-side USB peripheral core written in Verilog.☆236Updated 3 years ago
- RISC-V CPU Core☆405Updated 7 months ago
- VeeR EL2 Core☆316Updated last month
- Small footprint and configurable Ethernet core☆272Updated 2 weeks ago
- SystemVerilog to Verilog conversion☆698Updated 2 months ago
- A DDR3 memory controller in Verilog for various FPGAs☆555Updated 4 years ago
- ☆305Updated last week
- Documenting the Xilinx 7-series bit-stream format.☆847Updated 7 months ago
- ☆258Updated 3 years ago
- A Linux-capable RISC-V multicore for and by the world☆758Updated 2 weeks ago
- RISC-V Debug Support for our PULP RISC-V Cores☆291Updated last month
- A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …☆696Updated last week
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆487Updated last week
- CORE-V Family of RISC-V Cores☆320Updated 11 months ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆456Updated 8 months ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆563Updated 3 months ago
- Common SystemVerilog components☆704Updated last month