VLSI EDA Global Router
☆85Feb 15, 2026Updated 6 months ago
Alternatives and similar repositories for nthu-route
Users that are interested in nthu-route are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- nthu-route 2.11☆14Aug 5, 2019Updated 7 years ago
- CUGR, VLSI Global Routing Tool Developed by CUHK☆154Feb 27, 2023Updated 3 years ago
- Global Router Built for ICCAD Contest 2019☆35Mar 20, 2020Updated 6 years ago
- BoxRouter2.0 is a new global router for ultimate routability. It is inspired by BoxRouter [1], but can perform multi-layer routing with 2…☆22Dec 20, 2018Updated 7 years ago
- Dr. CU, VLSI Detailed Routing Tool Developed by CUHK☆150Mar 20, 2023Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆62Aug 10, 2020Updated 6 years ago
- Steiner Shallow-Light Tree for VLSI Routing☆63Jul 11, 2024Updated 2 years ago
- Standard cell placement (global and detailed) tool based on modified algorithm “simulated annealing”☆12Jan 7, 2026Updated 8 months ago
- An analytical VLSI placer☆31Nov 22, 2021Updated 4 years ago
- Deep learning toolkit-enabled VLSI placement☆1,047Jul 18, 2026Updated last month
- Rsyn – An Extensible Physical Synthesis Framework☆140Jul 20, 2024Updated 2 years ago
- Applying Deep Q-learning for Global Routing☆133Sep 15, 2020Updated 5 years ago
- Some simple examples for the Magic VLSI physical chip layout tool.☆31Mar 9, 2021Updated 5 years ago
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆198May 19, 2025Updated last year
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).☆62Aug 7, 2022Updated 4 years ago
- REST, a reinforcement learning framework for constructing rectilinear Steiner Minimum tree (RSMT)☆62Apr 22, 2022Updated 4 years ago
- EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!☆76Jan 6, 2023Updated 3 years ago
- VLSI placement and routing tool☆15Dec 20, 2025Updated 8 months ago
- A parallel global router using the Galois framework☆31Apr 6, 2026Updated 5 months ago
- Code for new techniques of VLSI placement☆13Oct 11, 2013Updated 12 years ago
- Implementations of DeepPlace, PRNet, HubRouter, PreRoutGNN, FlexPlanner and DSBRouter.☆322Nov 23, 2025Updated 9 months ago
- genetic algorithm usage for routing optimization ( pyqt )☆15Mar 24, 2019Updated 7 years ago
- Database and Tool Framework for EDA☆127Jan 25, 2021Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Training a deep FCN network in PyTorch to route circuit layouts☆68Dec 7, 2022Updated 3 years ago
- UCSD Detailed Router☆98Jan 5, 2021Updated 5 years ago
- RePlAce global placement tool☆255Aug 13, 2020Updated 6 years ago
- ILP SAT Detailed Router☆13Apr 14, 2020Updated 6 years ago
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆116Mar 9, 2024Updated 2 years ago
- GDSII File Parsing, IC Layout Analysis, and Parameter Extraction☆136Apr 23, 2023Updated 3 years ago
- ☆103Jun 26, 2019Updated 7 years ago
- ☆14Oct 23, 2018Updated 7 years ago
- autorouter forked from https://www-soc.lip6.fr/git/coriolis.git☆15May 21, 2018Updated 8 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Pathfinder routing algorithm practice☆15May 2, 2017Updated 9 years ago
- A High-performance Timing Analysis Tool for VLSI Systems☆716Dec 26, 2025Updated 8 months ago
- Incremental Timing-Driven Placement, problem C of ICCAD contest 2015☆16Sep 28, 2017Updated 8 years ago
- Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization☆170Jul 8, 2026Updated last month
- 🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit☆184Apr 25, 2025Updated last year
- Flute3 is an open-source rectilinear Steiner minimum tree heuristic from Iowa State, with UFRGS improvements☆31Dec 16, 2020Updated 5 years ago
- NTHU CS6135 VLSI Physical Design Automation Course Projects (include Two-way Min-cut Partitioning, Fixed-outline Slicing Floorplan Design…☆43Sep 7, 2025Updated last year