luckyrantanplan / nthu-routeLinks
VLSI EDA Global Router
☆79Updated 7 years ago
Alternatives and similar repositories for nthu-route
Users that are interested in nthu-route are comparing it to the libraries listed below
Sorting:
- CUGR, VLSI Global Routing Tool Developed by CUHK☆141Updated 2 years ago
- Dr. CU, VLSI Detailed Routing Tool Developed by CUHK☆141Updated 2 years ago
- Rsyn – An Extensible Physical Synthesis Framework☆136Updated last year
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆189Updated 8 months ago
- UCSD Detailed Router☆94Updated 5 years ago
- Open Source Detailed Placement engine☆40Updated 6 years ago
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆59Updated 5 years ago
- Global Router Built for ICCAD Contest 2019☆33Updated 5 years ago
- RePlAce global placement tool☆246Updated 5 years ago
- Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization☆150Updated 7 months ago
- DATC Robust Design Flow.☆36Updated 5 years ago
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆108Updated last year
- DATC RDF☆50Updated 5 years ago
- BoxRouter2.0 is a new global router for ultimate routability. It is inspired by BoxRouter [1], but can perform multi-layer routing with 2…☆21Updated 7 years ago
- Collection of digital hardware modules & projects (benchmarks)☆75Updated last month
- Database and Tool Framework for EDA☆122Updated 4 years ago
- ☆32Updated 4 years ago
- 🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit☆167Updated 8 months ago
- ☆35Updated 5 years ago
- Assignments of Physical Design for Nanometer ICs (Spring 2017, Prof. Yao-Wen Chang)☆44Updated 7 years ago
- NTHU CS6135 VLSI Physical Design Automation Course Projects (include Two-way Min-cut Partitioning, Fixed-outline Slicing Floorplan Design…☆42Updated 4 months ago
- ☆48Updated 2 years ago
- Pin-Accessible Legalization for Mixed-Cell-Height Circuits☆31Updated 3 years ago
- GPU-based logic synthesis tool☆97Updated last month
- ☆109Updated 6 years ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆61Updated last year
- A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).☆59Updated 3 years ago
- A LEF/DEF Utility.☆33Updated 6 years ago
- Steiner Shallow-Light Tree for VLSI Routing☆61Updated last year
- ☆78Updated 2 weeks ago