luckyrantanplan / nthu-route
VLSI EDA Global Router
☆72Updated 7 years ago
Alternatives and similar repositories for nthu-route:
Users that are interested in nthu-route are comparing it to the libraries listed below
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆54Updated 4 years ago
- CUGR, VLSI Global Routing Tool Developed by CUHK☆133Updated 2 years ago
- Open Source Detailed Placement engine☆38Updated 5 years ago
- Global Router Built for ICCAD Contest 2019☆31Updated 5 years ago
- DATC Robust Design Flow.☆37Updated 5 years ago
- DATC RDF☆50Updated 4 years ago
- A parallel global router using the Galois framework☆27Updated last year
- Rsyn – An Extensible Physical Synthesis Framework☆125Updated 9 months ago
- Dr. CU, VLSI Detailed Routing Tool Developed by CUHK☆133Updated 2 years ago
- UCSD Detailed Router☆85Updated 4 years ago
- Steiner Shallow-Light Tree for VLSI Routing☆51Updated 9 months ago
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆102Updated last year
- Assignments of Physical Design for Nanometer ICs (Spring 2017, Prof. Yao-Wen Chang)☆40Updated 6 years ago
- Delay Calculation ToolKit☆31Updated 2 years ago
- ☆30Updated 4 years ago
- ☆18Updated last year
- Pin-Accessible Legalization for Mixed-Cell-Height Circuits☆27Updated 3 years ago
- An analytical VLSI placer☆28Updated 3 years ago
- Routing Visualization for Physical Design☆19Updated 6 years ago
- BoxRouter2.0 is a new global router for ultimate routability. It is inspired by BoxRouter [1], but can perform multi-layer routing with 2…☆21Updated 6 years ago
- Xplace 2.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability Optimization☆121Updated 4 months ago
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆157Updated 4 months ago
- A LEF/DEF Utility.☆28Updated 5 years ago
- ☆10Updated 3 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- Timing prediction dataset download and instructions.☆15Updated last year
- EDA physical synthesis optimization kit☆53Updated last year
- GPU-based logic synthesis tool☆81Updated 9 months ago
- A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).☆55Updated 2 years ago
- Artificial Netlist Generator☆38Updated last year