The-OpenROAD-Project-Attic / flute3Links
Flute3 is an open-source rectilinear Steiner minimum tree heuristic from Iowa State, with UFRGS improvements
☆29Updated 4 years ago
Alternatives and similar repositories for flute3
Users that are interested in flute3 are comparing it to the libraries listed below
Sorting:
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆58Updated 5 years ago
- VLSI EDA Global Router☆75Updated 7 years ago
- Dr. CU, VLSI Detailed Routing Tool Developed by CUHK☆137Updated 2 years ago
- UCSD Detailed Router☆91Updated 4 years ago
- CUGR, VLSI Global Routing Tool Developed by CUHK☆138Updated 2 years ago
- REST, a reinforcement learning framework for constructing rectilinear Steiner Minimum tree (RSMT)☆57Updated 3 years ago
- ☆17Updated 5 years ago
- Steiner Shallow-Light Tree for VLSI Routing☆58Updated last year
- ☆33Updated 5 years ago
- BoxRouter2.0 is a new global router for ultimate routability. It is inspired by BoxRouter [1], but can perform multi-layer routing with 2…☆21Updated 6 years ago
- Analog Placement Quality Prediction☆24Updated 2 years ago
- DATC RDF☆50Updated 5 years ago
- An analytical VLSI placer☆28Updated 3 years ago
- SAGERoute: Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility (DATE2023)☆22Updated 2 years ago
- Global Router Built for ICCAD Contest 2019☆32Updated 5 years ago
- Annealing-based PCB placement tool☆39Updated 5 years ago
- Power grid analysis☆19Updated 5 years ago
- the awesome work, project and lab of EDA (Electronic Design Automation). continue update...☆24Updated last year
- Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization☆139Updated 4 months ago
- Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".☆52Updated 4 months ago
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆181Updated 5 months ago
- Pin-Accessible Legalization for Mixed-Cell-Height Circuits☆30Updated 3 years ago
- ☆34Updated 4 years ago
- Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)☆78Updated last year
- RePlAce global placement tool☆239Updated 5 years ago
- A LEF/DEF Utility.☆32Updated 6 years ago
- DATC Robust Design Flow.☆36Updated 5 years ago
- Rsyn – An Extensible Physical Synthesis Framework☆132Updated last year
- IO and Pin Placer for Floorplan-Placement Subflow☆22Updated 5 years ago
- ☆58Updated 4 years ago