ywtseng / NTUPlacement

Related projects ⓘ

Alternatives and complementary repositories for NTUPlacement

• UTDA-group / BoxRouter
  BoxRouter2.0 is a new global router for ultimate routability. It is inspired by BoxRouter [1], but can perform multi-layer routing with 2…
  ☆20Updated 5 years ago
• geziangfinn / easyPlace
  Reimplementation of the VLSI placement algorithm: ePlace and ePlace-MS
  ☆19Updated last week
• cuhk-eda / ripple
  Pin-Accessible Legalization for Mixed-Cell-Height Circuits
  ☆26Updated 2 years ago
• ABKGroup / PlacementEssentialReadings
  ☆49Updated 3 years ago
• cuhk-eda / REST
  REST, a reinforcement learning framework for constructing rectilinear Steiner Minimum tree (RSMT)
  ☆50Updated 2 years ago
• mgwoo / RePlAce
  ☆10Updated 2 years ago
• PKU-IDEA / SAGERoute
  SAGERoute: Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility (DATE2023)
  ☆19Updated last year
• ABKGroup / TritonRoute-WXL
  ☆25Updated 4 years ago
• magical-eda / UT-AnLay
  Analog Placement Quality Prediction
  ☆19Updated last year
• cuhk-eda / cu-gr
  CUGR, VLSI Global Routing Tool Developed by CUHK
  ☆121Updated last year
• LQY404 / EDA-info
  the awesome work, project and lab of EDA (Electronic Design Automation). continue update...
  ☆19Updated 2 months ago
• AUCOHL / OGRE
  Global Router Built for ICCAD Contest 2019
  ☆30Updated 4 years ago
• cuhk-eda / Xplace
  Xplace 2.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability Optimization
  ☆97Updated 4 months ago
• jinwookjungs / datc_robust_design_flow
  DATC Robust Design Flow.
  ☆37Updated 4 years ago
• The-OpenROAD-Project-Attic / FastRoute
  LEF/DEF-based port of Iowa State's open-source FastRoute 4.1
  ☆52Updated 4 years ago
• cuhk-eda / dr-cu
  Dr. CU, VLSI Detailed Routing Tool Developed by CUHK
  ☆128Updated last year
• PKU-IDEA / MacroRank
  Official implementation of MacroRank: Ranking Macro Placement Solutions Leveraging Translation Equivariancy (ASP-DAC 2023)
  ☆16Updated last year
• baloneymath / AncstrGNN
  ☆15Updated 3 years ago
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆48Updated 4 years ago
• EricLu1218 / Physical_Design_Automation
  2019 NTHU CS6135 (CS613500) VLSI Physical Design Automation Course Projects (include Two-way Min-cut Partitioning, Fixed-outline Slicing …
  ☆29Updated 10 months ago
• daeyeon22 / artificial_netlist_generator
  Artificial Netlist Generator
  ☆32Updated 7 months ago
• The-OpenROAD-Project / TritonRoute
  UCSD Detailed Router
  ☆79Updated 3 years ago
• liangrj2014 / ISPD24_contest
  ☆20Updated last month
• RsynTeam / rsyn-x
  Rsyn – An Extensible Physical Synthesis Framework
  ☆122Updated 3 months ago
• luckyrantanplan / nthu-route
  VLSI EDA Global Router
  ☆68Updated 6 years ago
• zslwyuan / AMF-Placer
  AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…
  ☆97Updated 8 months ago
• asyncvlsi / SPRoute
  A parallel global router using the Galois framework
  ☆25Updated last year
• cuhk-eda / cu-gr-2
  ☆35Updated 10 months ago
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆67Updated 3 months ago
• hkust-zhiyao / APPLE
  A circuit-element level explainer to explain machine learning model's prediction on chip layouts.
  ☆17Updated last year