jacky860226 / nthu-routeLinks
nthu-route 2.11
☆13Updated 6 years ago
Alternatives and similar repositories for nthu-route
Users that are interested in nthu-route are comparing it to the libraries listed below
Sorting:
- VLSI EDA Global Router☆75Updated 7 years ago
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆58Updated 5 years ago
- BoxRouter2.0 is a new global router for ultimate routability. It is inspired by BoxRouter [1], but can perform multi-layer routing with 2…☆21Updated 6 years ago
- NTHU CS6135 VLSI Physical Design Automation Course Projects (include Two-way Min-cut Partitioning, Fixed-outline Slicing Floorplan Design…☆42Updated 2 months ago
- Courseworks of CS6165 VLSI Physical Design Automation, NTHU.☆49Updated 4 years ago
- Dr. CU, VLSI Detailed Routing Tool Developed by CUHK☆138Updated 2 years ago
- Reimplementation of the VLSI placement algorithm: ePlace and ePlace-MS☆53Updated last year
- Rsyn – An Extensible Physical Synthesis Framework☆132Updated last year
- CUGR, VLSI Global Routing Tool Developed by CUHK☆138Updated 2 years ago
- Analog Placement Quality Prediction☆25Updated 2 years ago
- Open Source Detailed Placement engine☆39Updated 5 years ago
- ☆34Updated 5 years ago
- ☆13Updated 2 years ago
- Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization☆142Updated 4 months ago
- REST, a reinforcement learning framework for constructing rectilinear Steiner Minimum tree (RSMT)☆58Updated 3 years ago
- DATC RDF☆50Updated 5 years ago
- Pin-Accessible Legalization for Mixed-Cell-Height Circuits☆30Updated 3 years ago
- Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)☆82Updated last year
- Benchmark Generator for Global Routing☆12Updated 6 years ago
- ☆47Updated last year
- Assignments of Physical Design for Nanometer ICs (Spring 2017, Prof. Yao-Wen Chang)☆43Updated 6 years ago
- UCSD Detailed Router☆91Updated 4 years ago
- Global Router Built for ICCAD Contest 2019☆32Updated 5 years ago
- This is a deep-learning based model for Electronic Design Automation(EDA), predicting the IR drop location on the chip.☆32Updated 2 years ago
- ☆59Updated 4 years ago
- Must-read papers on Graph Neural Networks (GNNs) for Integrated Circuits (ICs) design, security and reliability.☆68Updated 3 months ago
- Timing prediction dataset download and instructions.☆15Updated 2 years ago
- A parallel global router using the Galois framework☆30Updated 2 years ago
- ☆23Updated last year
- ☆11Updated last year