Alternatives and similar repositories for SimAn

Users that are interested in SimAn are comparing it to the libraries listed below

• aziesemer / astran
  ASTRAN - Automatic Synthesis of Transistor Networks
  ☆66Updated 3 years ago
• chengengjie / salt
  Steiner Shallow-Light Tree for VLSI Routing
  ☆62Updated last year
• mgraczyk / coursera-vlsicad
  Programming assignments for Coursera's U of I VLSI CAD: Logic to Layout
  ☆14Updated 11 years ago
• abhowmick22 / atpg-PODEM
  Automatic Test Pattern Generation using PODEM algorithm
  ☆15Updated 11 years ago
• Coloquinte / Coloquinte_placement
  An analytical VLSI placer
  ☆30Updated 4 years ago
• luckyrantanplan / nthu-route
  VLSI EDA Global Router
  ☆80Updated 8 years ago
• clin99 / awesome-eda
  ☆95Updated 6 years ago
• sanggido / OpenDP
  Open Source Detailed Placement engine
  ☆40Updated 6 years ago
• asyncvlsi / AMC
  AMC: Asynchronous Memory Compiler
  ☆52Updated 5 years ago
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆50Updated 5 years ago
• Daikon-Sun / Routing-Visualization
  Routing Visualization for Physical Design
  ☆20Updated 7 years ago
• purdue-onchip / gds2Para
  GDSII File Parsing, IC Layout Analysis, and Parameter Extraction
  ☆129Updated 2 years ago
• parallella / openeda
  Open source EDA chip design flow
  ☆51Updated 8 years ago
• ckchengucsd / SMT-based-STDCELL-Layout-Generator
  SMT-based-STDCELL-Layout-Generator
  ☆18Updated 4 years ago
• scale-lab / OpenPhySyn
  EDA physical synthesis optimization kit
  ☆64Updated 2 years ago
• The-OpenROAD-Project / OpenRCX
  ☆24Updated 5 years ago
• limbo018 / Limbo
  Library for VLSI CAD Design Useful parsers and solvers' api are implemented.
  ☆190Updated 8 months ago
• OpenTimer / Parser-SPEF
  A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
  ☆59Updated 3 years ago
• The-OpenROAD-Project / asap5
  ☆38Updated 2 years ago
• pkuzjx / eda-collection
  ☆109Updated 6 years ago
• jinwookjungs / lefdef_util
  A LEF/DEF Utility.
  ☆33Updated 6 years ago
• andrsmllr / magic_vlsi_examples
  Some simple examples for the Magic VLSI physical chip layout tool.
  ☆30Updated 4 years ago
• jinwookjungs / datc_robust_design_flow
  DATC Robust Design Flow.
  ☆36Updated 6 years ago
• yellekelyk / PyVerilog
  Python-based Verilog Parser (currently Netlist only)
  ☆54Updated 8 years ago
• skuep / GDS3D
  Fork from https://sourceforge.net/projects/gds3d
  ☆68Updated last year
• The-OpenROAD-Project / TritonCTS
  Source codes and calibration scripts for clock tree synthesis
  ☆40Updated 5 years ago
• circuitgraph / circuitgraph
  Tools for working with circuits as graphs in python
  ☆126Updated 2 years ago
• sgherbst / msdsl
  Automatic generation of real number models from analog circuits
  ☆48Updated last year
• ucb-art / BAG_framework
  ☆160Updated 3 years ago
• christophmuellerorg / spectre_python
  Simple and most probably incomplete parser for spectre netlists
  ☆14Updated 9 years ago