en9inerd / SimAnLinks
Standard cell placement (global and detailed) tool based on modified algorithm “simulated annealing”
☆12Updated last year
Alternatives and similar repositories for SimAn
Users that are interested in SimAn are comparing it to the libraries listed below
Sorting:
- An analytical VLSI placer☆28Updated 3 years ago
- Open source EDA chip design flow☆51Updated 8 years ago
- VLSI EDA Global Router☆75Updated 7 years ago
- Steiner Shallow-Light Tree for VLSI Routing☆58Updated last year
- Programming assignments for Coursera's U of I VLSI CAD: Logic to Layout☆14Updated 11 years ago
- Automatic Test Pattern Generation using PODEM algorithm☆13Updated 11 years ago
- ☆94Updated 6 years ago
- Routing Visualization for Physical Design☆19Updated 6 years ago
- ASTRAN - Automatic Synthesis of Transistor Networks☆65Updated 3 years ago
- This library contains rectilinear spanning graph construction, finding minimum spanning tree and an implementation of binary search tree☆10Updated 10 years ago
- EDA physical synthesis optimization kit☆62Updated last year
- An open multiple patterning framework☆79Updated last year
- GDSII File Parsing, IC Layout Analysis, and Parameter Extraction☆127Updated 2 years ago
- Open Source Detailed Placement engine☆39Updated 5 years ago
- ☆22Updated 4 years ago
- DATC RDF☆50Updated 5 years ago
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆183Updated 5 months ago
- OpenDesign Flow Database☆16Updated 7 years ago
- SMT-based-STDCELL-Layout-Generator☆18Updated 4 years ago
- A LEF/DEF Utility.☆32Updated 6 years ago
- ☆35Updated 2 years ago
- Magic VLSI Layout Tool☆21Updated 6 years ago
- Python-based Verilog Parser (currently Netlist only)☆54Updated 8 years ago
- EDA Analytics Central☆17Updated 2 years ago
- A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).☆57Updated 3 years ago
- Global Router Built for ICCAD Contest 2019☆32Updated 5 years ago
- This library is a low level parser for the GDSII file format.☆36Updated 8 years ago
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆58Updated 5 years ago
- A custom C++ routine to identify logic gates in the layout extracted netlist (SPICE) of digital circuits and generate gate-level Verilog …☆31Updated last year
- UCSD Detailed Router☆91Updated 4 years ago