EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!
☆75Jan 6, 2023Updated 3 years ago
Alternatives and similar repositories for EDAViewer
Users that are interested in EDAViewer are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A LEF/DEF Utility.☆34Aug 15, 2019Updated 6 years ago
- Technology file parser in Rust☆13Apr 6, 2021Updated 4 years ago
- VLSI EDA Global Router☆81Feb 15, 2026Updated last month
- Database and Tool Framework for EDA☆124Jan 25, 2021Updated 5 years ago
- GDSII File Parsing, IC Layout Analysis, and Parameter Extraction☆129Apr 23, 2023Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- RePlAce global placement tool☆248Aug 13, 2020Updated 5 years ago
- Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format☆13Feb 13, 2020Updated 6 years ago
- A High-performance Timing Analysis Tool for VLSI Systems☆694Dec 26, 2025Updated 3 months ago
- DATC RDF☆49Jul 31, 2020Updated 5 years ago
- Incremental Timing-Driven Placement, problem C of ICCAD contest 2015☆15Sep 28, 2017Updated 8 years ago
- Some simple examples for the Magic VLSI physical chip layout tool.☆30Mar 9, 2021Updated 5 years ago
- Global Router Built for ICCAD Contest 2019☆34Mar 20, 2020Updated 6 years ago
- DATC Robust Design Flow.☆35Jan 21, 2020Updated 6 years ago
- Rsyn – An Extensible Physical Synthesis Framework☆138Jul 20, 2024Updated last year
- NordVPN Special Discount Offer • AdSave on top-rated NordVPN 1 or 2-year plans with secure browsing, privacy protection, and support for for all major platforms.
- Annealing-based PCB placement tool☆43May 26, 2020Updated 5 years ago
- ☆10Jun 30, 2021Updated 4 years ago
- Selected problems and their solutions from the book on "Machine Intelligence in Design Automation"☆27Dec 9, 2018Updated 7 years ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆34Dec 25, 2025Updated 3 months ago
- ☆17Jun 24, 2021Updated 4 years ago
- Yosys plugin for synthesis of Bluespec code☆15Sep 8, 2021Updated 4 years ago
- Open SoC Debug Hardware Reference Implementation☆16Jul 15, 2019Updated 6 years ago
- Free open source EDA tools☆66Oct 1, 2019Updated 6 years ago
- A complete open-source design-for-testing (DFT) Solution☆183Aug 30, 2025Updated 7 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting with the flexibility to host WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Cloudways by DigitalOcean.
- Miscellaneous components for bluespec☆11Nov 18, 2024Updated last year
- Deep learning toolkit-enabled VLSI placement☆963Feb 19, 2026Updated last month
- autorouter forked from https://www-soc.lip6.fr/git/coriolis.git☆15May 21, 2018Updated 7 years ago
- Source code for LEF/DEF☆11Oct 16, 2018Updated 7 years ago
- Dr. CU, VLSI Detailed Routing Tool Developed by CUHK☆142Mar 20, 2023Updated 3 years ago
- Parser and Viewer for Cadence® Library Exchange Format (LEF) and Design Exchange Format (DEF) integrated circuit (IC) description languag…☆17May 31, 2023Updated 2 years ago
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆194May 19, 2025Updated 10 months ago
- Ophidian's Mirror Repository on github. https://gitlab.com/eclufsc/eda/ophidian☆45Feb 17, 2021Updated 5 years ago
- Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.☆89May 7, 2024Updated last year
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- Workshop on Open-Source EDA Technology (WOSET)☆48Nov 18, 2024Updated last year
- Mirror of the Si2 LEF/DEF parser (v5.8)☆19Oct 8, 2021Updated 4 years ago
- Static timing analysis (STA) is a method of validating the timing performance of a design by checking all possible paths for timing viola…☆16Oct 4, 2022Updated 3 years ago
- A Xtext based SystemRDL editor with syntax highlighting and context sensitive help☆12Feb 9, 2024Updated 2 years ago
- Contains commonly used UVM components (agents, environments and tests).☆32Aug 17, 2018Updated 7 years ago
- Material for OpenROAD Tutorial at DAC 2020☆46Dec 8, 2022Updated 3 years ago
- OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/☆2,524Updated this week