Alternatives and similar repositories for pyqt_genetic_algo

Users that are interested in pyqt_genetic_algo are comparing it to the libraries listed below

• sysu-eda / DeepRL-Scheduling
  A Deep-Reinforcement-Learning-Based Scheduler for FPGA HLS
  ☆15Updated 4 years ago
• EDAAC / EDAAC
  EDA Analytics Central
  ☆16Updated 2 years ago
• Daikon-Sun / Routing-Visualization
  Routing Visualization for Physical Design
  ☆19Updated 6 years ago
• haiguanl / GlobalRoutingProblemGenerator
  Benchmark Generator for Global Routing
  ☆12Updated 6 years ago
• srohit0 / mida
  Selected problems and their solutions from the book on "Machine Intelligence in Design Automation"
  ☆27Updated 6 years ago
• mflowgen / skywater-130nm
  ASIC Design kit for Skywater 130 for use with mflowgen
  ☆13Updated 2 years ago
• wvangansbeke / High-Level-Synthesis
  Convert C files into Verilog
  ☆17Updated 6 years ago
• shalan / AD_SAR_ADC
  Digital Standard Cells based SAR ADC
  ☆14Updated 4 years ago
• cgfandia / PathfinderAlgorithm
  Pathfinder routing algorithm practice
  ☆15Updated 8 years ago
• IntelLabs / parsac
  This is the implementation of the Parallel Simulated Annealing with Constraints (PARSAC) algorithm
  ☆15Updated 2 months ago
• jinwookjungs / datc_robust_design_flow
  DATC Robust Design Flow.
  ☆36Updated 5 years ago
• SubZer0811 / verilog_grapher
  Graph your gate-level verilog code as a directed graph!
  ☆18Updated 4 years ago
• electronics-and-drives / MLCAD22
  Source code for the Paper: "Deep Reinforcement Learning for Analog Circuit Sizing with an Electrical Design Space and Sparse Rewards"
  ☆13Updated 2 years ago
• The-OpenROAD-Project / PcbRouter
  ☆33Updated 5 years ago
• snishizawa / asap7_snps
  Supplemental technology files for ASAP7 PDK with Synopsys design flow
  ☆17Updated 2 years ago
• EDAPack / edapack
  Provides a packaged collection of open source EDA tools
  ☆12Updated 6 years ago
• The-OpenROAD-Project / PCB-PR-App
  ☆16Updated 5 years ago
• panhomyoung / phySAT
  Semi-Tenser Product based SAT and AllSAT solver, where it can solve CNF and circuit input.
  ☆16Updated 2 years ago
• AICPS / hw2vec
  ☆42Updated 2 years ago
• JKomp / AIGER
  Python version of tools to work with AIG formatted files
  ☆12Updated 3 months ago
• Chenghao-Yang / awesome-ml4ls
  Awesome machine learning for logic synthesis
  ☆29Updated 2 years ago
• jinwookjungs / lefdef_util
  A LEF/DEF Utility.
  ☆31Updated 6 years ago
• chengengjie / salt
  Steiner Shallow-Light Tree for VLSI Routing
  ☆56Updated last year
• ShonTaware / RISC-V_Core_4_Stage
  RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set
  ☆15Updated 4 years ago
• mgraczyk / coursera-vlsicad
  Programming assignments for Coursera's U of I VLSI CAD: Logic to Layout
  ☆12Updated 11 years ago
• lydiawunan / IronMan
  IronMan+alpha: Graph Neural Network and Reinforcement Learning in High-Level Synthesis
  ☆26Updated 3 years ago
• hadarshavit / revisiting_satzilla
  SATZilla SAT feature extraction tool
  ☆10Updated last year
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆50Updated 5 years ago
• haiguanl / DQN_GlobalRouting
  Applying Deep Q-learning for Global Routing
  ☆129Updated 4 years ago
• AUCOHL / OGRE
  Global Router Built for ICCAD Contest 2019
  ☆33Updated 5 years ago