Alternatives and similar repositories for pyqt_genetic_algo:

Users that are interested in pyqt_genetic_algo are comparing it to the libraries listed below

• cgfandia / PathfinderAlgorithm
  Pathfinder routing algorithm practice
  ☆12Updated 7 years ago
• khushhallchandra / Simulated-Annealing
  Simulated Annealing to minimize the wirelength
  ☆8Updated 7 years ago
• EDAAC / EDAAC
  EDA Analytics Central
  ☆15Updated 2 years ago
• Daikon-Sun / Routing-Visualization
  Routing Visualization for Physical Design
  ☆18Updated 6 years ago
• shalan / AD_SAR_ADC
  Digital Standard Cells based SAR ADC
  ☆12Updated 3 years ago
• haiguanl / GlobalRoutingProblemGenerator
  Benchmark Generator for Global Routing
  ☆12Updated 5 years ago
• mgraczyk / coursera-vlsicad
  Programming assignments for Coursera's U of I VLSI CAD: Logic to Layout
  ☆11Updated 10 years ago
• AUCOHL / OGRE
  Global Router Built for ICCAD Contest 2019
  ☆30Updated 4 years ago
• sysu-eda / DeepRL-Scheduling
  A Deep-Reinforcement-Learning-Based Scheduler for FPGA HLS
  ☆14Updated 3 years ago
• en9inerd / SimAn
  Standard cell placement (global and detailed) tool based on modified algorithm “simulated annealing”
  ☆10Updated 9 months ago
• scale-lab / OpenPhySyn
  EDA physical synthesis optimization kit
  ☆50Updated last year
• srohit0 / mida
  Selected problems and their solutions from the book on "Machine Intelligence in Design Automation"
  ☆26Updated 6 years ago
• jinwookjungs / datc_robust_design_flow
  DATC Robust Design Flow.
  ☆37Updated 5 years ago
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆49Updated 4 years ago
• nputikhin / sat_atpg
  SAT-based ATPG using TG-Pro model
  ☆16Updated 6 years ago
• The-OpenROAD-Project / PcbRouter
  ☆30Updated 4 years ago
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆18Updated 3 years ago
• scale-lab / BACS
  Benchmarks for Approximate Circuit Synthesis
  ☆15Updated 4 years ago
• electronics-and-drives / MLCAD22
  Source code for the Paper: "Deep Reinforcement Learning for Analog Circuit Sizing with an Electrical Design Space and Sparse Rewards"
  ☆11Updated 2 years ago
• jinwookjungs / open_design_flow
  OpenDesign Flow Database
  ☆16Updated 6 years ago
• sgherbst / msdsl
  Automatic generation of real number models from analog circuits
  ☆37Updated 10 months ago
• yellekelyk / PyVerilog
  Python-based Verilog Parser (currently Netlist only)
  ☆53Updated 7 years ago
• Coloquinte / Coloquinte_placement
  An analytical VLSI placer
  ☆28Updated 3 years ago
• The-OpenROAD-Project / TritonCTS
  Source codes and calibration scripts for clock tree synthesis
  ☆40Updated 5 years ago
• sanggido / OpenDP
  Open Source Detailed Placement engine
  ☆36Updated 5 years ago
• ckchengucsd / SMT-based-STDCELL-Layout-Generator-for-PROBE2.0
  SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0
  ☆16Updated 4 years ago
• leonardt / hwtypes
  Python implementations of fixed size hardware types (Bit, BitVector, UInt, SInt, ...) based on the SMT-LIB2 semantics
  ☆18Updated last year
• YuanTingHsieh / ITDP
  Incremental Timing-Driven Placement, problem C of ICCAD contest 2015
  ☆13Updated 7 years ago
• Kkalais / Hardware-Trojan-Detection
  Machine Learning Techniques for Hardware Trojan Detection
  ☆19Updated 4 years ago
• EDAPack / edapack
  Provides a packaged collection of open source EDA tools
  ☆12Updated 5 years ago