RePlAce global placement tool
☆246Aug 13, 2020Updated 5 years ago
Alternatives and similar repositories for RePlAce
Users that are interested in RePlAce are comparing it to the libraries listed below
Sorting:
- Deep learning toolkit-enabled VLSI placement☆947Feb 19, 2026Updated last week
- Rsyn – An Extensible Physical Synthesis Framework☆137Jul 20, 2024Updated last year
- Database and Tool Framework for EDA☆123Jan 25, 2021Updated 5 years ago
- Open Source Detailed Placement engine☆40Nov 27, 2019Updated 6 years ago
- IO and Pin Placer for Floorplan-Placement Subflow☆23Aug 11, 2020Updated 5 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Feb 18, 2020Updated 6 years ago
- Dr. CU, VLSI Detailed Routing Tool Developed by CUHK☆142Mar 20, 2023Updated 2 years ago
- UCSD Detailed Router☆96Jan 5, 2021Updated 5 years ago
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆60Aug 10, 2020Updated 5 years ago
- DATC Robust Design Flow.☆35Jan 21, 2020Updated 6 years ago
- UCSD Sizer for leakage/dynamic power recovery, timing recovery☆18Mar 5, 2019Updated 6 years ago
- CUGR, VLSI Global Routing Tool Developed by CUHK☆142Feb 27, 2023Updated 3 years ago
- Open Source Detailed Placement engine☆12Feb 19, 2020Updated 6 years ago
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆192May 19, 2025Updated 9 months ago
- RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA☆91Feb 11, 2020Updated 6 years ago
- An analytical VLSI placer☆31Nov 22, 2021Updated 4 years ago
- OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/☆2,450Updated this week
- Annealing-based PCB placement tool☆40May 26, 2020Updated 5 years ago
- A LEF/DEF Utility.☆33Aug 15, 2019Updated 6 years ago
- ☆15Oct 24, 2019Updated 6 years ago
- Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization☆156Jan 16, 2026Updated last month
- OpenSTA engine☆552Updated this week
- Pin-Accessible Legalization for Mixed-Cell-Height Circuits☆31Feb 25, 2022Updated 4 years ago
- ☆33Aug 23, 2022Updated 3 years ago
- Analog Placement Quality Prediction☆25Mar 24, 2023Updated 2 years ago
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆109Mar 9, 2024Updated last year
- DATC RDF☆49Jul 31, 2020Updated 5 years ago
- A High-performance Timing Analysis Tool for VLSI Systems☆690Dec 26, 2025Updated 2 months ago
- ☆339Jan 13, 2026Updated last month
- Macro placement tool for OpenROAD flow☆25Aug 13, 2020Updated 5 years ago
- Macro Placement - benchmarks, evaluators, and reproducible results from leading methods in open source☆301Jan 5, 2026Updated last month
- Open-sourced utilities for initial flow setup, calibration, and other user functions for OpenROAD project☆20Aug 20, 2019Updated 6 years ago
- Intel's Analog Detailed Router☆40Jul 18, 2019Updated 6 years ago
- Machine Generated Analog IC Layout☆270Apr 24, 2024Updated last year
- Builds, flow and designs for the alpha release☆54Dec 18, 2019Updated 6 years ago
- autorouter forked from https://www-soc.lip6.fr/git/coriolis.git☆15May 21, 2018Updated 7 years ago
- ☆10Mar 14, 2022Updated 3 years ago
- VLSI EDA Global Router☆80Feb 15, 2026Updated 2 weeks ago
- EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!☆73Jan 6, 2023Updated 3 years ago