purdue-onchip / gds2Para
GDSII File Parsing, IC Layout Analysis, and Parameter Extraction
☆117Updated last year
Alternatives and similar repositories for gds2Para:
Users that are interested in gds2Para are comparing it to the libraries listed below
- This library is a low level parser for the GDSII file format.☆32Updated 7 years ago
- A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).☆54Updated 2 years ago
- A Design Rule Checker with GPU Acceleration☆48Updated last year
- Python script to convert image files to GDSII files☆60Updated last week
- Fork from https://sourceforge.net/projects/gds3d☆68Updated 8 months ago
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆150Updated last month
- ☆22Updated 4 years ago
- Qrouter detail router for digital ASIC designs☆56Updated 4 months ago
- Intel's Analog Detailed Router☆38Updated 5 years ago
- GDS3D is an application that can interpret so called IC layouts and render them in 3D. The program accepts standard GDSII files as input …☆211Updated 6 months ago
- A simple but powerful Python package for creating photolithography masks in the GDSII format.☆92Updated last year
- An open multiple patterning framework☆72Updated 9 months ago
- BAG framework☆40Updated 6 months ago
- ☆37Updated 10 months ago
- Circuit release of the MAGICAL project☆31Updated 5 years ago
- BAG2 workspace for fake PDK (cds_ff_mpt)☆55Updated 4 years ago
- UCSD Detailed Router☆84Updated 4 years ago
- Parsing and generating popular formats of circuit netlist☆30Updated 2 years ago
- Parametric layout generator for digital, analog and mixed-signal integrated circuits☆52Updated last week
- Netgen complete LVS tool for comparing SPICE or verilog netlists☆113Updated last week
- GDS to ASCII Converter☆19Updated last year
- Cadence SKILL utilities that have boosted my productivity considerably for 10+ years.☆41Updated 3 months ago
- An OASIS and GDS2 (chip layout format) binary dump tool for debugging☆40Updated 7 years ago
- skywater 130nm pdk☆26Updated 4 months ago
- Python port of Prof. Boris Murmann's gm/ID Starter Kit☆53Updated 7 years ago
- Cadence Virtuoso Design Management System☆33Updated 2 years ago
- A Python and SKILL Framework for Cadence Virtuoso☆34Updated 11 months ago
- Circuit Automatic Characterization Engine☆47Updated 2 weeks ago
- Verilog-A simulation models☆64Updated last month
- KLayout technology files for Skywater SKY130☆39Updated last year