UTDA-group / BoxRouter

Related projects ⓘ

Alternatives and complementary repositories for BoxRouter

• AUCOHL / OGRE
  Global Router Built for ICCAD Contest 2019
  ☆30Updated 4 years ago
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆48Updated 4 years ago
• jinwookjungs / datc_robust_design_flow
  DATC Robust Design Flow.
  ☆37Updated 4 years ago
• magical-eda / UT-AnLay
  Analog Placement Quality Prediction
  ☆19Updated last year
• The-OpenROAD-Project-Attic / FastRoute
  LEF/DEF-based port of Iowa State's open-source FastRoute 4.1
  ☆52Updated 4 years ago
• asyncvlsi / SPRoute
  A parallel global router using the Galois framework
  ☆26Updated last year
• The-OpenROAD-Project / TritonRoute
  UCSD Detailed Router
  ☆80Updated 3 years ago
• luckyrantanplan / nthu-route
  VLSI EDA Global Router
  ☆69Updated 6 years ago
• ABKGroup / TritonRoute-WXL
  ☆26Updated 4 years ago
• cuhk-eda / ripple
  Pin-Accessible Legalization for Mixed-Cell-Height Circuits
  ☆26Updated 2 years ago
• ABKGroup / PROBE_SMT_AutoCell
  ☆17Updated last year
• cuhk-eda / cu-gr
  CUGR, VLSI Global Routing Tool Developed by CUHK
  ☆123Updated last year
• sanggido / OpenDP
  Open Source Detailed Placement engine
  ☆34Updated 4 years ago
• baloneymath / AncstrGNN
  ☆15Updated 3 years ago
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆69Updated 4 months ago
• abk-openroad / BST-DME
  Bounded-Skew DME v1.3
  ☆14Updated 6 years ago
• cuhk-eda / cu-gr-2
  ☆36Updated 10 months ago
• ywtseng / NTUPlacement
  ☆11Updated 6 years ago
• daeyeon22 / artificial_netlist_generator
  Artificial Netlist Generator
  ☆33Updated 8 months ago
• cuhk-eda / dr-cu
  Dr. CU, VLSI Detailed Routing Tool Developed by CUHK
  ☆128Updated last year
• ABKGroup / PlacementEssentialReadings
  ☆50Updated 3 years ago
• ALIGN-analoglayout / AnalogDetailedRouter
  Intel's Analog Detailed Router
  ☆37Updated 5 years ago
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆36Updated last month
• RsynTeam / rsyn-x
  Rsyn – An Extensible Physical Synthesis Framework
  ☆122Updated 4 months ago
• geziangfinn / easyPlace
  Reimplementation of the VLSI placement algorithm: ePlace and ePlace-MS
  ☆19Updated 3 weeks ago
• liangrj2014 / ISPD24_contest
  ☆20Updated last month
• PKU-IDEA / SAGERoute
  SAGERoute: Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility (DATE2023)
  ☆19Updated last year
• jinwookjungs / lefdef_util
  A LEF/DEF Utility.
  ☆27Updated 5 years ago
• mgwoo / RePlAce
  ☆10Updated 2 years ago
• TimingPredict / Dataset
  Timing prediction dataset download and instructions.
  ☆13Updated last year