Alternatives and similar repositories for VLSIPlacement

Users that are interested in VLSIPlacement are comparing it to the libraries listed below

• dokelung / minickt
  Analyzer and simulator of logic circuit
  ☆15Updated 8 years ago
• shininglion / rectilinear_spanning_graph
  This library contains rectilinear spanning graph construction, finding minimum spanning tree and an implementation of binary search tree
  ☆10Updated 10 years ago
• shininglion / corner_stitch
  Library of corner stitching structure
  ☆17Updated 10 years ago
• Coloquinte / Coloquinte_placement
  An analytical VLSI placer
  ☆28Updated 3 years ago
• pabennett / ethernet_mac
  A VHDL implementation of an Ethernet MAC
  ☆15Updated 13 years ago
• The-OpenROAD-Project-Attic / ioPlacer
  IO and Pin Placer for Floorplan-Placement Subflow
  ☆22Updated 5 years ago
• libresilicon / magic-8.2
  Magic VLSI Layout Tool
  ☆21Updated 5 years ago
• SymbiFlow / vtr-verilog-to-routing
  SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆38Updated last year
• The-OpenROAD-Project / OpenDP
  Open Source Detailed Placement engine
  ☆12Updated 5 years ago
• Poofjunior / fpga_fast_serial_sort
  a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially
  ☆41Updated 9 years ago
• en9inerd / SimAn
  Standard cell placement (global and detailed) tool based on modified algorithm “simulated annealing”
  ☆12Updated last year
• warclab / dyract
  DyRACT Open Source Repository
  ☆16Updated 9 years ago
• torc-isi / torc
  Torc: Tools for Open Reconfigurable Computing
  ☆39Updated 8 years ago
• abhowmick22 / atpg-PODEM
  Automatic Test Pattern Generation using PODEM algorithm
  ☆13Updated 11 years ago
• aziesemer / astran
  ASTRAN - Automatic Synthesis of Transistor Networks
  ☆64Updated 3 years ago
• pabennett / chiptools
  ChipTools is a utility to automate FPGA build and verification
  ☆24Updated 3 years ago
• The-OpenROAD-Project / TritonCTS
  Source codes and calibration scripts for clock tree synthesis
  ☆40Updated 5 years ago
• steveicarus / ivtest
  Regression test suite for Icarus Verilog. (OBSOLETE)
  ☆115Updated 2 years ago
• apertus-open-source-cinema / alpha-software
  Axiom Alpha prototype software (FPGA, Linux, etc.)
  ☆30Updated 9 years ago
• jbush001 / PASC
  Parallel Array of Simple Cores. Multicore processor.
  ☆99Updated 6 years ago
• parallella / openeda
  Open source EDA chip design flow
  ☆51Updated 8 years ago
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆18Updated 3 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 9 years ago
• ZipCPU / videozip
  A ZipCPU SoC for the Nexys Video board supporting video functionality
  ☆18Updated 10 months ago
• ccelio / riscv-boom-doc
  Documentation for the BOOM processor
  ☆47Updated 8 years ago
• sveditor / sveditor
  SystemVerilog Development Environment
  ☆54Updated 4 years ago
• clothbot / Alliance-VLSI-CAD-System
  Git repository to manage the fixes I need to make to the alliance-5.0-20090901 source for Mac OS X compiles.
  ☆17Updated 15 years ago
• strezh / XPDMA
  PCIe DMA Subsystem based on Xilinx XAPP1171
  ☆47Updated 2 years ago
• openrisc / or1ksim
  The OpenRISC 1000 architectural simulator
  ☆76Updated 4 months ago
• grantae / mips32r1_core
  A 32-bit MIPS processor which aims for conformance to the MIPS32 Release 1 ISA.
  ☆19Updated 10 years ago