nakultirumalai / VLSIPlacement
Code for new techniques of VLSI placement
☆12Updated 11 years ago
Alternatives and similar repositories for VLSIPlacement:
Users that are interested in VLSIPlacement are comparing it to the libraries listed below
- IO and Pin Placer for Floorplan-Placement Subflow☆22Updated 4 years ago
- Open Source Detailed Placement engine☆11Updated 4 years ago
- Macro placement tool for OpenROAD flow☆23Updated 4 years ago
- An analytical VLSI placer☆27Updated 3 years ago
- Standard cell placement (global and detailed) tool based on modified algorithm “simulated annealing”☆10Updated 8 months ago
- Magic VLSI Layout Tool☆21Updated 5 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 4 years ago
- Design of a 32-kbit synchronous SRAM with 32-bit words, using 180 nm process technology. Developed MATLAB scripts to evaluate architectu…☆15Updated 3 years ago
- This library contains rectilinear spanning graph construction, finding minimum spanning tree and an implementation of binary search tree☆9Updated 9 years ago
- Open Source Detailed Placement engine☆35Updated 5 years ago
- DyRACT Open Source Repository☆16Updated 8 years ago
- Programming assignments for Coursera's U of I VLSI CAD: Logic to Layout☆11Updated 10 years ago
- Open source EDA chip design flow☆49Updated 7 years ago
- SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research☆37Updated 4 months ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated last year
- Accelerating a Classic 3D Video Game (The DOOM) on Heterogeneous Reconfigurable MPSoCs☆16Updated 4 years ago
- Welcome to Birds-of-a-Feather: Open-Source-Academic-EDA-Software !☆12Updated 5 years ago
- Steiner Shallow-Light Tree for VLSI Routing☆48Updated 6 months ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆28Updated 6 months ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆52Updated 4 years ago
- Power grid analysis☆19Updated 4 years ago
- Global Router Built for ICCAD Contest 2019☆29Updated 4 years ago
- VLSI EDA Global Router☆70Updated 6 years ago
- Collection of test cases for Yosys☆18Updated 3 years ago
- Si2 LEF parser☆9Updated 4 years ago
- A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).☆54Updated 2 years ago
- Benchmarks for Yosys development☆23Updated 4 years ago
- OpenDesign Flow Database☆16Updated 6 years ago
- ☆28Updated 4 years ago