andrsmllr / magic_vlsi_examples
Some simple examples for the Magic VLSI physical chip layout tool.
☆29Updated 4 years ago
Alternatives and similar repositories for magic_vlsi_examples:
Users that are interested in magic_vlsi_examples are comparing it to the libraries listed below
- ☆20Updated 3 years ago
- Minimal SKY130 example with self-checking LVS, DRC, and PEX☆23Updated 4 years ago
- ☆40Updated 3 years ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆30Updated 3 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆44Updated 3 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- This script builds openlane and all its dependencies on an Ubuntu (only) System.☆21Updated 2 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆65Updated 4 years ago
- SystemVerilog RTL Linter for YoSys☆20Updated 4 months ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆66Updated 3 years ago
- ☆16Updated 2 years ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆44Updated 4 years ago
- ☆25Updated 2 weeks ago
- ☆14Updated 3 years ago
- Open source process design kit for 28nm open process☆51Updated 11 months ago
- ☆43Updated 5 years ago
- Physical Design Flow from RTL to GDS using Opensource tools.☆95Updated 4 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆38Updated 3 years ago
- An open source PDK using TIGFET 10nm devices.☆48Updated 2 years ago
- XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.☆61Updated this week
- Design of 4KB(1024*32) SRAM with operating voltage 1.8v and access time < 2.5ns☆12Updated 4 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- Design of Analog Blocks in Skywaters 130nm meeting corners: different flavors of OTA, BandGap, LDO.☆26Updated 2 years ago
- Design of 4KB Static RAM 1.8V (access time <2.5ns) using OpenRAM and Sky130 node☆14Updated 3 years ago
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 4 years ago
- BAG framework☆40Updated 8 months ago
- A set of Python based parsers for multiple file format used in IC chip design, including Verilog, SPICE, lib (Synopsys Liberty).☆31Updated 9 years ago
- KLayout technology files for Skywater SKY130☆39Updated last year
- ☆12Updated 2 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆38Updated 4 years ago