Framework Open EDA Gui
☆75Dec 11, 2024Updated last year
Alternatives and similar repositories for FOEDAG
Users that are interested in FOEDAG are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Raptor end-to-end FPGA Compiler and GUI☆101Dec 11, 2024Updated last year
- This is a SpyDrNet Plugin for a physical design related transformations☆16Oct 18, 2026Updated 2 weeks ago
- FPGA tool performance profiling☆108Feb 24, 2024Updated 2 years ago
- An Open-source FPGA IP Generator☆1,167Updated this week
- A flexible framework for analyzing and transforming FPGA netlists. Official repository.☆117Apr 27, 2026Updated 6 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆13Jun 10, 2026Updated 4 months ago
- Open-source EDA framework for RTL elaboration, netlist analysis, and transformation, with C++ and Python APIs☆169Updated this week
- IP Catalog for Raptor.☆18Dec 6, 2024Updated last year
- Project 1.1 Simulate a Skywater 130nm standard cell using ngspice☆14Jul 18, 2025Updated last year
- Content for the FPGA Primer Course offered by the OSFPGA Foundation, Redwood EDA, and VLSI System Design.☆42Jul 3, 2023Updated 3 years ago
- An easy-to-use, silicon-proven (e)FPGA generator with an integrated CAD toolchain 🏗️☆313Updated this week
- SystemVerilog synthesis tool☆237Mar 10, 2025Updated last year
- IDEA project source files☆115Apr 15, 2026Updated 6 months ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆155Mar 17, 2023Updated 3 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Plugins for Yosys developed as part of the F4PGA project.☆85May 14, 2024Updated 2 years ago
- FOSS Flow For FPGA☆454Jan 6, 2025Updated last year
- List of Machine Learning Technical AI Blogs☆13Dec 22, 2025Updated 10 months ago
- A list of resources related to the open-source FPGA projects☆467Nov 26, 2022Updated 3 years ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆270Updated this week
- ☆26Feb 15, 2025Updated last year
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆21Feb 25, 2023Updated 3 years ago
- HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-sla…☆27Sep 28, 2026Updated last month
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆116Mar 9, 2024Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Project 2.2 Frequency counter☆12May 30, 2025Updated last year
- ☆12Jul 22, 2022Updated 4 years ago
- Cross compile FPGA tools☆21Jan 4, 2021Updated 5 years ago
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 features☆32Jan 30, 2025Updated last year
- Site for NUS Hackers Hackerschool☆12Feb 7, 2024Updated 2 years ago
- A bit-serial CPU☆20Sep 29, 2019Updated 7 years ago
- Hdl21 Schematics☆17Jan 24, 2024Updated 2 years ago
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,282Updated this week
- ORPSoC fork (from git://openrisc.net/stefan/orpsoc) for de0_nano board with custom made expansion board☆12Sep 26, 2013Updated 13 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Online documentation can be found at https://minres.github.io/SCViewer/☆22Aug 17, 2026Updated 2 months ago
- Build Customized FPGA Implementations for Vivado☆397Updated this week
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆478Updated this week
- Slides from C++ on Sea 2025☆15Aug 5, 2025Updated last year
- ☆13Updated this week
- A DSL for formal verification of hardware and software systems using Rocq/Coq.☆13Updated this week
- ☆15Mar 6, 2021Updated 5 years ago