Alternatives and similar repositories for FOEDAG:

Users that are interested in FOEDAG are comparing it to the libraries listed below

• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆74Updated last week
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆75Updated 2 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆65Updated 6 months ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated 10 months ago
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆71Updated 8 months ago
• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆76Updated 3 months ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆59Updated last year
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆81Updated 2 weeks ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆60Updated 3 weeks ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆119Updated 3 weeks ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• The-OpenROAD-Project / megaboom
  ☆25Updated 2 weeks ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆69Updated 2 years ago
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆33Updated last month
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆64Updated last month
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆115Updated this week
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆134Updated 2 weeks ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆34Updated 3 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆130Updated 2 months ago
• hypernyan / eth_vlg
  ☆61Updated 3 years ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆63Updated 3 months ago
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆50Updated 7 months ago
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆43Updated 4 months ago
• xver / Shunt
  SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)
  ☆43Updated last month
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆49Updated last year
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆52Updated 10 months ago
• OSVVM / Documentation
  OSVVM Documentation
  ☆33Updated this week
• OpenTimer / Parser-Verilog
  A Standalone Structural Verilog Parser
  ☆89Updated 3 years ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆102Updated 3 years ago