Alternatives and similar repositories for FOEDAG

Users that are interested in FOEDAG are comparing it to the libraries listed below

• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆78Updated 5 months ago
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆74Updated this week
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆76Updated 2 years ago
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆59Updated 3 years ago
• OSVVM / Documentation
  OSVVM Documentation
  ☆33Updated last week
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆54Updated 2 years ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆64Updated 2 weeks ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆65Updated 8 months ago
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆71Updated 10 months ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆103Updated this week
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆65Updated 4 months ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆131Updated last week
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆60Updated 2 years ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆116Updated this week
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆64Updated last week
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆56Updated 6 months ago
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆50Updated last week
• chipsalliance / uvm-verilator
  ☆92Updated last year
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆136Updated last month
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆93Updated 3 weeks ago
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆66Updated 7 months ago
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆34Updated 5 months ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆49Updated last year
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆52Updated 11 months ago
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆58Updated 3 months ago
• shariethernet / RPHAX
  RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…
  ☆18Updated 2 years ago
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆30Updated last week