Alternatives and similar repositories for FOEDAG:

Users that are interested in FOEDAG are comparing it to the libraries listed below

• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆80Updated 8 months ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆61Updated 2 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆65Updated 4 months ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆111Updated last month
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆55Updated last month
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆130Updated last month
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆67Updated 6 months ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆56Updated last year
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆79Updated 2 months ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆82Updated 3 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆125Updated this week
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆71Updated 6 months ago
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆72Updated this week
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆33Updated last week
• verilator / verilator-announce
  Announcements related to Verilator
  ☆38Updated 4 years ago
• vsdip / vsdsram_sky130
  ☆40Updated 2 years ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools
  ☆156Updated this week
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆56Updated 3 years ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆75Updated 2 years ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆69Updated last week
• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆73Updated last month
• efabless / caravel_user_project_analog
  ☆45Updated last month
• FPGA-Systems / drawio-hdl-builder
  Drawio => VHDL and Verilog
  ☆51Updated last year
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆54Updated 3 months ago
• missinglinkelectronics / fpga-vbs
  Vivado build system
  ☆66Updated last month
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆48Updated 4 months ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆54Updated 2 years ago
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆41Updated 2 months ago