os-fpga / FOEDAGLinks
Framework Open EDA Gui
☆73Updated 11 months ago
Alternatives and similar repositories for FOEDAG
Users that are interested in FOEDAG are comparing it to the libraries listed below
Sorting:
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- Sphinx Extension which generates various types of diagrams from Verilog code.☆63Updated 2 years ago
- Extensible FPGA control platform☆61Updated 2 years ago
- A flexible framework for analyzing and transforming FPGA netlists. Official repository.☆102Updated 9 months ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆76Updated 3 months ago
- Raptor end-to-end FPGA Compiler and GUI☆90Updated 11 months ago
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆21Updated 2 years ago
- Python script to transform a VCD file to wavedrom format☆81Updated 3 years ago
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments☆69Updated last month
- Test dashboard for verification features in Verilator☆28Updated last week
- FuseSoC standard core library☆148Updated 5 months ago
- Drawio => VHDL and Verilog☆61Updated 2 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆118Updated 2 years ago
- FPGA tool performance profiling☆103Updated last year
- Simple parser for extracting VHDL documentation☆72Updated last year
- ☆31Updated 2 years ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆62Updated 4 years ago
- Determines the modules declared and instantiated in a SystemVerilog file☆48Updated last year
- Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.☆101Updated 9 months ago
- Streaming based VHDL parser.☆84Updated last year
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆125Updated 5 months ago
- ☆38Updated 3 years ago
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆218Updated this week
- ☆87Updated last month
- ☆44Updated 5 years ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆142Updated 2 years ago
- A SystemVerilog source file pickler.☆60Updated last year
- Structural Netlist API (and more) for EDA post synthesis flow development☆120Updated this week
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆62Updated last week
- Bitstream relocation and manipulation tool.☆49Updated 2 years ago